Mpc8240 Integrated Processor Core Block Diagram - Motorola MPC8240 User Manual

Overview
SYSTEM
REGISTER
UNIT
+
INTEGER
UNIT
/ +
*
XER
COMPLETION
UNIT
Power Time Base
Dissipation
Control Decrementer
JTAG/COP
Interface
Figure 5-1. MPC8240 Integrated Processor Core Block Diagram
5-2
SEQUENTIAL
FETCHER
64 Bit
INSTRUCTION
QUEUE
Dispatch Unit
64 Bit
32 Bit
LOAD/STORE
GPR File
UNIT
GP Rename
Registers
+
D MMU
SRs
DTLB
Counter/
Tags
Clock
Multiplier
Touch Load Buffer
Copyback Buffer
32-BIT ADDRESS BUS
32-/64-BIT DATA BUS
MPC8240 Integrated Processor User's Manual
BRANCH
64 Bit
PROCESSING
UNIT
CTR
CR
LR
64 Bit
INSTRUCTION UNIT
64 Bit 64 Bit
FPR File
FP Rename
Registers
32 Bit
DBAT
64 Bit
Array
16-Kbyte
D Cache
PERIPHERAL LOGIC
BUS INTERFACE
64 Bit
FLOATING-
POINT UNIT
+
/
*
FPSCR
I MMU
SRs
IBAT
Array
ITLB
16-Kbyte
Tags
I Cache