Example Fpm Debug Address, Miv, And Maa Timings For Burst Write - Motorola MPC8240 User Manual

Memory Interface Valid (MIV)
SDRAM_CLK[0:3]
RAS/CS[0:7]
CAS/DQM[0:7]
ADDRESS
DATA
WE
DEBUG ADDRESS
MIV
MAA
NOTES
:
1. Subscripts identify programmable timing variables (RP 1 , RCD 2 , CAS 3 ).
2. MIV asserts for address, control, and data on the first clock cycle that RAS or CAS is asserted
for a write.
Figure 15-9. Example FPM Debug Address, MIV, and MAA Timings for Burst Write
15-10
RP
1
RC
CAS
CRP RCD
2
CP
CSH
ROW COL
ASR RAH ASC CAH
DATA0
DS
RAD
WCS
WCH
VALID
Operation
MPC8240 Integrated Processor User's Manual
RASP
CP CAS CP
3 4 5 4
PC
COL COL
CAH
DATA1 DATA2
DH DS DH
WP
WCS WCH
VALID
VALID
CAS CP CAS
5 4 5
RSH
COL
RAL
RHCP
DATA3
VALID VALID