Motorola MPC8240 User Manual page 209

is encountered. However, in many cases there is no attempt to re-execute the instruction.
This method of recognizing and handling exception conditions sequentially guarantees that
exceptions are recoverable.
Exception handlers should save the information stored in SRR0 and SRR1 early to prevent
the program state from being lost due to a system reset or machine check exception or to
an instruction-caused exception in the exception handler. SRR0 and SRR1 should also be
saved before enabling external interrupts.
The PowerPC architecture supports four types of exceptions:
• Synchronous, precise—These are caused by instructions. All instruction-caused
exceptions are handled precisely; that is, the machine state at the time the exception
occurs is known and can be completely restored. This means that (excluding the trap
and system call exceptions) the address of the faulting instruction is provided to the
exception handler and neither the faulting instruction nor subsequent instructions in
the code stream will complete execution before the exception is taken. Once the
exception is processed, execution resumes at the address of the faulting instruction
(or at an alternate address provided by the exception handler). When an exception is
taken due to a trap or system call instruction, execution resumes at an address
provided by the handler.
• Synchronous, imprecise—The PowerPC architecture defines two imprecise
floating-point exception modes, recoverable and nonrecoverable. These are not
implemented on the MPC8240.
• Asynchronous, maskable—The external interrupt (int), system management
interrupt (SMI), and decrementer interrupts are maskable asynchronous exceptions.
When these exceptions occur, their handling is postponed until the next instruction
and any exceptions associated with that instruction complete execution. If no
instructions are in the execution units, the exception is taken immediately upon
determination of the correct restart address (for loading SRR0).
• Asynchronous, nonmaskable—There are two nonmaskable asynchronous
exceptions— system reset and the machine check exception. These exceptions may
not be recoverable, or may provide a limited degree of recoverability. All exceptions
report recoverability through MSR[RI].
5.5.2 MPC8240 Implementation-Specific Exception Model
As specified by the PowerPC architecture, all processor core exceptions can be described
as either precise or imprecise and either synchronous or asynchronous. Asynchronous
exceptions (some of which are maskable) are caused by events external to the processor's
execution. Synchronous exceptions, which are all handled precisely by the processor core,
are caused by instructions. The processor core exception classes are shown in Table 5-7.
Chapter 5. PowerPC Processor Core
Exception Model
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