Internal Processor Bus Error Status Register—0Xc3 - Motorola MPC8240 User Manual

Table 4-31. Bit Settings for Error Detection Register 1 (ErrDR1)—0xC1 (Continued)
Bits Name
2 Memory read parity
error/ECC single-bit
error trigger exceeded
1–0 Unsupported
processor transaction
The processor bus error status register (BESR) latches the state of the internal processor
address attributes when an internal bus error is detected. This information then can be used
by error handling software. Figure 4-23 shows the bits of the processor bus error status
register and Table 4-32 provides a detailed description of the bit settings.
Figure 4-23. Internal Processor Bus Error Status Register—0xC3
U
Table 4-32. Bit Settings for Internal Processor Bus Error Status Register—0xC3
Reset
Bits Name
Value
7–3 TT[0:4] 0000_0
2–0 TSIZ[0:2] 000
Figure 4-24 shows the enable bits for ErrEnR2.
PCI Address Parity Error Enable
Figure 4-24. Error Enabling Register 2 (ErrEnR2)—0xC4
Reset
Value
0 Memory read parity error/ECC single-bit error trigger exceeded
0 No error detected
1 Parity error detected or ECC single-bit error trigger exceeded
00 Unsupported processor transaction
00 No error detected
01 Unsupported transfer attributes. Refer to Chapter 13, "Error Handling,"
for more details.
10 Reserved
11 Reserved
TT[0:4]
7
These bits maintain a copy of TT[0:4]. When a processor bus error is detected, these
bits are latched until all error flags are cleared.
These bits maintain a copy of TSIZ[0:2]. When a processor bus error is detected,
these bits are latched until all error flags are cleared.
0 0 0
7 6
Chapter 4. Configuration Registers
Description
TSIZ[0:2]
3 2 0
Description
4 3 2 1 0
Error Handling Registers
Reserved
ECC Multibit Error Enable
Processor/Memory Write
Parity Error Enable
PCI Received Target Abort
Error Enable
Flash ROM Write Error
Enable
4-37