Watchpoint Trigger Registers - Motorola MPC8240 User Manual

Watchpoint Registers

16.2.2 Watchpoint Trigger Registers

Watchpoint triggers are set based on a subset of the peripheral logic bus that includes the
32-bit address bus and 26 control signals. These watchpoints are compared with the values
on the peripheral logic bus on every clock cycle. There are separate sets of trigger registers
for watchpoints #1 and #2. These registers are read/write and initialized to 0x0000_0000
on reset.
Figure 16-2 and Figure 16-3 show the format of the watchpoint #1 and watchpoint #2
control trigger registers (WP1_CNTL_TRIG and WP2_CNTL_TRIG). Note that the
format of these two registers is identical, but they are shown separately to emphasize that
their location is at different offsets.
0000_00
31 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Figure 16-2. Watchpoint #1 Control Trigger Register (WP1_CNTL_TRIG)—
0000_00
31 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Figure 16-3. Watchpoint #1 Control Trigger Register (WP1_CNTL_TRIG)—
Table 16-3 shows the bit definitions for WP1_CNTL_TRIG and WP2_CNTL_TRIG.
Table 16-3. Watchpoint Control Trigger Register Bit Field Definitions
Bits Name Reset Value
31–26 — 0b000_000
25 QREQ_ 0
24 QACK_ 0
23 BR_ 0
22 BG_ 0
21 TS_ 0
16-4
TT0[0:4] TSIZ[0:2]
Offsets 0xF_F018, 0xF18
TT0[0:4] TSIZ[0:2]
Offsets 0xF_F030, 0xF30
R/W
R Reserved
R/W 0 Trigger if QREQ asserted on peripheral logic bus
1 Trigger if QREQ negated
R/W 0 Trigger if QACK asserted on peripheral logic bus
1 Trigger if QACK negated
RW 0 Trigger if BR asserted on peripheral logic bus
1 Trigger if BR negated
RW 0 Trigger if BG asserted on peripheral logic bus
1 Trigger if BG negated
R/W 0 Trigger if TS asserted on peripheral logic bus
1 Trigger if TS negated
9 8 7 6 5 4
9 8 7 6 5 4
Description
3 2 1 0
3 2 1 0