Motorola MPC8240 User Manual page 638

ARn, 2-21
AS, 2-23
CASn, 2-17
CKE, 2-21
CSn, 2-17
DQMn, 2-17
FOE, 2-23
PARn (data parity/ECC), 2-20
RASn, 2-16
RCSn (ROM bank select), 2-22
SDCAS, 2-22
SDRAS, 2-21
signal summary, 6-3
WE, 2-18
MIV, 1-20, 2-31, 15-8
output signal states at power-on reset, 2-7
PCI address attribute signals, 15-3
PCI attribute signals, 1-20
PCI interface
ADn, 2-9, 7-12
C/BEn, 2-10, 7-31
description, 2-7
DEVSEL, 2-11, 7-13
FRAME, 2-12, 7-9
GNT, 2-8, 7-4
INTA Interrupt request, 2-15
IRDY, 2-12, 7-9
LOCK, 2-13, 7-29
PAR (PCI parity), 2-10, 7-31
PERR, 2-14, 7-32, 13-5
REQ, 2-8, 7-4
SERR, 2-14, 7-32
STOP, 2-15, 7-14
TRDY, 2-13, 7-9
turnaround cycle, 7-14
PMAA, 2-30
power management
QACK, 2-28
signal groupings, 2-3
SMI, 2-28
system control
description, 2-25
HRESET, 13-3
MCP, 2-27
NMI, 2-27, 13-5, 13-11
SRESET, 2-26
TBEN, 2-28
test and configuration
description, 2-31, 15-21
IEEE 1149.1 interface, 15-21
PLL_CFG, 2-31
TCK (JTAG test clock), 2-31, 15-21
TDI (JTAG test data input), 2-32, 15-21
TDO (JTAG test data output), 2-32, 15-21
Index-14
INDEX
MPC8240 Integrated Processor User's Manual
TMS (JTAG test mode select), 2-32, 15-21
TRST (JTAG test reset), 2-32, 15-21
Sleep mode, 1-18
overview, 1-18
PMCR bit settings, 4-17
SMI (system management interrupt), 2-28
Snooping
snoop response, 12-8
SPRG0–SPRG3, conventional uses, E-18
SRESET (soft reset), 2-26
SRR0/SRR1 (status save/restore registers)
format, E-19, E-19
Status register, PCI, 7-13, 7-22, 7-31
STOP signal, 2-15, 7-14
String instructions, D-22
SVR (spurious vector) register, 11-19
Synchronization
memory synchronization instructions, D-22
System control signals, see Signals
System linkage instructions, D-24
System management interrupt, 14-2
System reset exception, 13-3
T
Target-abort error, 13-10
Target-disconnect, see PCI interface
Target-initiated termination
description, 7-2, 7-18
PCI status register, 7-18
TBEN (time base enable) signal, 2-28
TCK (JTAG test clock) signal, 2-31, 15-21
TDI (JTAG test data input) signal, 2-32, 15-21
TDO (JTAG test data output) signal, 2-32, 15-21
Termination
60x
termination by TEA, 13-10
PCI
completion, 7-17
master-abort termination, 7-17, 13-10
target-disconnect, 7-2, 7-18, 12-4
target-initiated, 7-18
termination of PCI transaction, 7-17
timeout, 7-17
Test and configuration signals, see Signals, 2-31
TFRR (timer frequency reporting) register, 11-20
Time base
computing time of day, E-11
reading the time base, E-10
TBL/TBU, E-10
writing to the time base, E-19
Timeout, PCI transaction, 7-17
Timer frequency reporting register, 11-20
TLB
invalidate, D-25