Inbound Fifo Queue Port Register (Ifqpr) - Motorola MPC8240 User Manual

Figure 9-6 shows the bits of the OMIMR.
0 0 0 0_0 0 0 0_0 0 0 0_0 0 0 0_0 0 0 0_0 0 0 0_0 0
31
Figure 9-6. Outbound Message Interrupt Mask Register (OMIMR)
Table 9-10 shows the bit settings for the OMIMR.
Table 9-10. OMIMR Field Descriptions—Offset 0x034
Bits Name
31–6 —
5 OPQIM
4 —
3 ODIM
2 —
1 OM1IM
0 OM0IM

9.3.4.1.3 Inbound FIFO Queue Port Register (IFQPR)

The IFQPR is used by PCI masters to access inbound messages in local memory. Figure 9-7
shows the bits of the IFQPR.
31
Figure 9-7. Inbound FIFO Queue Port Register (IFQPR)
Reset
R/W
Value
All 0s R Reserved
0 R/W Outbound post queue interrupt mask
0 Outbound post queue interrupt is allowed.
1 Outbound post queue interrupt is masked.
0 R Reserved
0 R/W Outbound doorbell interrupt mask
0 Outbound doorbell interrupt is allowed.
1 Outbound doorbell interrupt is masked.
0 R Reserved
0 R/W Outbound message 1 interrupt mask
0 Outbound message 1 interrupt is allowed.
1 Outbound message 1 interrupt is masked.
0 R/W Outbound message 0 interrupt mask
0 Outbound message 0 interrupt is allowed.
1 Outbound message 0 interrupt is masked.
Chapter 9. Message Unit (with I
OM0IM
OM1IM
ODIM
OPQIM
Description
IFQP
O)
2
I O Interface
2
Reserved
0 0
6 5 4 3 2 1 0
0
9-11