Motorola MPC8240 User Manual page 24

Figure
Number
4-12 Memory Ending Address Register 2-0x94............................................................... 4-25
4-13 Extended Memory Ending Address Register 1-0x98............................................... 4-26
4-14 Extended Memory Ending Address Register 2-0x9C .............................................. 4-26
4-15 Memory Bank Enable Register-0xA0 ...................................................................... 4-27
4-16 Memory Page Mode Register-0xA3 ........................................................................ 4-28
4-17 Processor Interface Configuration Register 1 (PICR1)-0xA8.................................. 4-29
4-18 Processor Interface Configuration Register 2 (PICR2)-0xAC................................. 4-31
4-19 ECC Single-Bit Error Counter Register-0xB8 ......................................................... 4-33
4-20 ECC Single-Bit Error Trigger Register-0xB9.......................................................... 4-34
4-21 Error Enabling Register 1 (ErrEnR1)-0xC0............................................................. 4-35
4-22 Error Detection Register 1 (ErrDR1)-0xC1 ............................................................. 4-36
4-23 Internal Processor Bus Error Status Register-0xC3 ................................................. 4-37
4-24 Error Enabling Register 2 (ErrEnR2)-0xC4............................................................. 4-37
4-25 Error Detection Register 2 (ErrDR2)-0xC5 ............................................................. 4-39
4-26 PCI Bus Error Status Register-0xC7........................................................................ 4-40
4-27 Processor/PCI Error Address Register-0xC8 ........................................................... 4-40
4-28 Address Map B Options Register (AMBOR)-0xE0................................................. 4-41
4-29 Memory Control Configuration Register 1 (MCCR1)-0xF0 ................................... 4-43
4-30 Memory Control Configuration Register 2 (MCCR2)-0xF4 ................................... 4-45
4-31 Memory Control Configuration Register 3 (MCCR3)-0xF8 ................................... 4-48
4-32 Memory Control Configuration Register 4 (MCCR4)-0xFC................................... 4-51
5-1 MPC8240 Integrated Processor Core Block Diagram .................................................. 5-2
5-2 MPC8240 Programming Model-Registers............................................................... 5-12
5-3 Hardware Implementation Register 0 (HID0) ............................................................ 5-13
5-4 Hardware Implementation Register 1 (HID1) ............................................................ 5-16
5-5 Hardware Implementation-Dependent Register 2 (HID2).......................................... 5-17
5-6 Data Cache Organization ............................................................................................ 5-22
6-1 Block Diagram for Memory Interface .......................................................................... 6-3
6-2 SDRAM Memory Interface Block Diagram................................................................. 6-6
6-3 Example 512-MByte SDRAM Configuration With Parity........................................... 6-8
6-4 SDRAM Flow-Through Memory Interface ................................................................ 6-14
6-5 SDRAM Registered Memory Interface ...................................................................... 6-15
6-6 . SDRAM In-line ECC/Parity Memory Interface ....................................................... 6-15
6-7 PGMAX Parameter Setting for SDRAM Interface .................................................... 6-20
6-8 SDRAM Single-Beat Read Timing (SDRAM Burst Length = 4) .............................. 6-23
6-9 SDRAM Four-Beat Burst Read Timing Configuration-64-Bit Mode ..................... 6-23
6-10 SDRAM Eight-Beat Burst Read Timing Configuration-32-Bit Mode .................... 6-24
6-11 SDRAM Single Beat Write Timing (SDRAM Burst Length = 4).............................. 6-24
6-12 SDRAM Four-Beat Burst Write Timing-64-Bit Mode ............................................ 6-25
6-13 SDRAM Eight-Beat Burst Write Timing-32-Bit Mode........................................... 6-25
6-14 SDRAM Mode Register Set Timing........................................................................... 6-26
6-15 Registered SDRAM DIMM Single-Beat Write Timing ............................................. 6-30
6-16 Registered SDRAM DIMM Burst-Write Timing ....................................................... 6-30
xxiv
ILLUSTRATIONS
Title
MPC8240 Integrated Processor User's Manual
Page
Number