Motorola MPC8240 User Manual page 628

EPIC unit
features list, 11-2
internal block diagram, 11-9
interrupt protocol, 11-7
overview, 1-16, 11-1
pass-through capability, 11-10
programming interface, 11-13
registers, 11-16
EICR, 11-17
EPIC EVI (vendor indentification), 11-18
external registers
IDRs (direct interrupt destination), 11-25
IVPRs (direct interrupt vector/priority), 11-25
SDRs (serial interrupt destination), 11-25
SVPRs (serial interrupt vector/priority), 11-25
FPR, 11-16
GCR, 11-16
GTBCR, 11-21
GTCCR, 11-21
GTDRs, 11-23
GTVPR, 11-22
IACK, 11-27
internal registers
IIDRs (internal interrupt destination), 11-26
IIVPRs (internal interrupt source), 11-26
non-programmable registers
IPR, 11-9
IRR, 11-10
IS, 11-9
ISR, 11-10
PCTPR, 11-27
PI, 11-19
SVR, 11-19
TFRR, 11-20
serial interrupt interface, 11-11
signals, 11-2
timers, 11-13
ErrDR1/ErrDR2 (error detection)
registers, 4-35, 7-30, 13-5
ErrEnR1/ErrEnR2 (error enabling) registers, 4-34
Error handling registers, 4-33
Error signals, see Errors
Errors
bus error status registers, 4-39
EDO ECC, 6-62
error detection registers, 4-35, 7-30, 13-5
error enabling registers, 4-34
error handling
overview, 13-1
registers, 2-27, 4-33, 7-30, 13-4
error reporting, 13-6
address/data error, 13-9
address/data parity errors, 7-19
error detection registers, 4-35, 7-30, 13-5
Index-4
INDEX
MPC8240 Integrated Processor User's Manual
errors within a nibble, 13-8
Flash write error, 13-7
master-abort transaction termination, 13-10
nonmaskable interrupt, 13-11
overflow condition, 4-35
PCI bus, 7-30, 13-4
PERR and SERR signals, 7-32, 13-4
system memory errors, 13-8
target-initiated termination, 7-18
TEA and MCP signals, 2-27
unsupported bus transaction error, 13-6
error reporting signals, see Signals, system
control, 2-27
error status registers, 13-6
FPM ECC, 6-62
overflow condition, 13-9
PCI interface
address/data parity errors, 7-32
error transactions, 7-30
processor bus error status registers, 7-30
retry transactions, 7-18
SDRAM ECC, 6-27
target-abort error, 7-18
target-disconnect error, 7-18
ESCR1/ESCR2 (emulation support configuration)
registers, 4-41
Exceptions
bus errors, 2-27, 13-4
interrupt and error signals, 13-3
interrupt latencies, 13-11
interrupt priorities, 13-2
overview, 5-26
system reset exception, 13-3
Exclusive access, PCI, 7-29
Execution units, 5-6
External control instructions, D-26
External direct interrupt vector/priority registers
(IVPRs), 11-25
External serial interrupt vector/priority registers
(SVPRs), 11-25
F
Features lists
debug features, 1-19
EPIC unit, 11-2
2
I C interface, 10-1
peripheral logic, 1-11
processor core, 5-3
Flash interface
address multiplexing, 6-77
operation, 6-73
overview, 6-73
timing, 6-78
write operations, 6-83