Outbound Fifo Queue Port Register (Ofqpr) - Motorola MPC8240 User Manual

I O Interface
2
Table 9-11 shows the bit settings for the IFQPR.
Table 9-11. IFQPR Field Descriptions—Offset 0x040
Reset
Bits Name
Value
31–0 IFQP All 0s

9.3.4.1.4 Outbound FIFO Queue Port Register (OFQPR)

The OFQPR is used by PCI masters to access outbound messages in local memory.
Figure 9-8 shows the bits of the OFQPR.
31
Figure 9-8. Outbound FIFO Queue Port Register (OFQPR)
Table 9-12 shows the bit settings for the OFQPR.
Table 9-12. OFQPR Field Descriptions—Offset 0x044
Reset
Bits Name
Value
31–0 OFQP All 0s
9.3.4.2 Processor-Accessible I
The following sections describe the I
of the bits that control the generic message and doorbell register interface in these registers.
9.3.4.2.1 Inbound Message Interrupt Status Register (IMISR)
The IMISR contains the interrupt status of the I
events. These events are routed to the processor core from the MU with the internal int or
mcp signals as described in Table 9-13. See Chapter 11, "Embedded Programmable
Interrupt Controller (EPIC) Unit," for more information about the assertion of int and
Chapter 13, "Error Handling," for more information about the enabling of machine check
exceptions to the processor core.
Writing a 1 to a set bit in IMISR clears the bit (except for read-only bits). The processor
core interrupt handling software must service these interrupts and clear these interrupt bits.
Software attempting to determine the source of the interrupts should always perform a
logical AND between the IMISR bits and their corresponding mask bits in the IMIMR. In
the case of doorbell machine check or interrupt conditions, the corresponding read-only bits
in IMISR (DMC and IDI) are cleared by writing a 0b1 to the corresponding machine check
and interrupt bits in IDBR (causing them to be cleared).
9-12
R/W
R/W Inbound FIFO queue port. Reading this register returns the MFA from the
inbound free_list FIFO. Writing to this register posts the MFA to the inbound
post_list FIFO.
R/W
R/W Outbound FIFO queue port. Reading this register returns the MFA from the
outbound post_list FIFO. Writing to this register posts the MFA to the outbound
free_list FIFO.
O registers accessible by the processor core and some
2
MPC8240 Integrated Processor User's Manual
Description
OFQP
Description
O Registers
2
O, doorbell register and message register
2
0