Motorola MPC8240 User Manual page 541

or r4, r4, r0
stwbrx r4,0,r6
//------ Embedded Unitility Memory Block Base Address Register( eumbbar )
addis r3,r0,BMC_BASE
ori r3,r3,0x0078
stwbrx r3,0,r5
lis r4,0xfc00// Don't forget to map this area
stwbrx r4,0,r6
sync
//! ===MCCR1=== MEMORY CONTROL CONFIGURATION
//!
addis r3,r0,BMC_BASE
ori r3,r3,0x00F0
stwbrx r3,0,r5
addis r4,r0,0x8800
ori r4,r4,0x0000// Set all banks to 64Mbit, 4 bank parts
stwbrx r4,0,r6
sync
//! ===MCCR2=== MEMORY CONTROL CONFIGURATION
//!
addis r3,r0,BMC_BASE// Set MCCR2 (F4)
ori r3,r3,0x00F4
stwbrx r3,0,r5
sync
lis r4, 0x0000
// ori r4, r4, 0x06b8
ori r4, r4, 0x023C
stwbrx r4,0,r6
sync
//! ===MCCR3=== MEMORY CONTROL CONFIGURATION
//!
addis r3,r0,BMC_BASE// Set MCCR3 (F8)
ori r3,r3,0x00F8
stwbrx r3,0,r5
sync
lis r4, 0x7840
ori r4, r4, 0x0000
stwbrx r4,0,r6
sync
//! ===MCCR4=== MEMORY CONTROL CONFIGURATION
//!
// EUMBBAR (78) = 0xFC00_0000
// into the BATs
// MCCR1 (F0) = 0x8800_0000
// Self-Refresh value
// 33 MHZ - REFINT
// 100 MHZ - REFINT
// RDLAT=4 (Mem CAS Latency+1), REFREC=1000,
// No EDO/FP parameters set (SDRAM)
Appendix C. Initialization Example C-3