Address Map B Pci Options In Host Mode - Motorola MPC8240 User Manual

Address Map B Options
Table 3-6. Address Map B—PCI Memory Master View in
PCI Memory Transaction Address Range
Hex
FD00_0000 FDFF_FFFF
FE00_0000 FEFF_FFFF
1. This address range is separately programmable (see Section 4.9, "Address Map B Options Register—0xE0")
for the processor interface and the PCI interface to control whether accesses to this address range go to local
memory or PCI memory.
2. If AMBOR[PCI_FD_ALIAS_EN] = 1 (see Section 4.9, "Address Map B Options Register—0xE0"), the
MPC8240 forwards PCI memory transactions in this range to local memory with the 8 most significant bits
cleared (that is, 0x00 || AD[23:0]).
3. The MPC8240 will respond to PCI memory cycles in the range PCSRBAR to PCSRBAR + 4 Kbytes (for runtime
registers). PCSRBAR can be programmed to be anywhere from 0x8000_0000 – 0xFCFF_FFFF or from
0xFE00_0000 – 0xFEFF_FFFF.
Figure 3-5 shows the optional PCI compatibility hole and PCI alias space in map B.
.
PCI Memory Space
0
640 KB
Compatibility Hole
1 MB
16 MB
4 GB - 48 MB
PCI alias space
4 GB - 32 MB
4G
Figure 3-5. Address Map B PCI Options in Host Mode
3-10
Host Mode Options (Continued)
Decimal
4G - 48M 4G - 32M - 1
4G - 32M 4G - 16M - 1
PCI transactions
PCI in the compatibility
hole are ignored by
the memory controller
PCI transactions
in the alias space
are translated to the
local memory space
MPC8240 Integrated Processor User's Manual
Local Memory
Address Range
0000_0000–00FF_FFFF
No local memory cycle
Processor
Core
Not accessible from PCI
Compatibility Hole
Definition
Local memory space
2
(16 Mbytes), 0-based
3
Reserved
View
0
640 KB
1 MB
16 MB
TOM
2G
4G