Motorola MPC8240 User Manual page 33

Table
Number
6-9 SDRAM System Configurations................................................................................. 6-14
6-10 MPC8240 SDRAM Interface Commands .................................................................. 6-18
6-11 SDRAM Interface Timing Intervals ........................................................................... 6-22
6-12 The MPC8240 SDRAM ECC Syndrome Encoding (Data Bits 0:31) ........................ 6-28
6-13 The MPC8240 SDRAM ECC Syndrome Encoding (Data Bits 32:63) ...................... 6-29
6-14 SDRAM Controller Power Saving Configurations..................................................... 6-34
6-15 SDRAM Power Saving Modes Refresh Configuration .............................................. 6-34
6-16 Unsupported Multiplexed Row and Column Address Bits......................................... 6-49
6-17 Supported FPM or EDO DRAM Device Configurations ........................................... 6-49
6-18 SDMA[11:8] Encodings for 32- and 64-Bit Bus Modes ............................................ 6-51
6-19 FPM or EDO Memory Parameters ............................................................................. 6-54
6-20 FPM or EDO System Configurations ......................................................................... 6-54
6-21 Memory Interface Configuration Register Fields ....................................................... 6-55
6-22 FPM or EDO Timing Parameters ............................................................................... 6-57
6-23 The MPC8240 FPM or EDO ECC Syndrome Encoding (Data bits 0:31).................. 6-63
6-24 The MPC8240 FPM or EDO ECC Syndrome Encoding (Data bits 32:63)................ 6-63
6-25 FPM or EDO DRAM Power Saving Modes Refresh Configuration.......................... 6-68
6-26 Reset Configurations of ROM/Flash Controller ......................................................... 6-76
7-1 PCI Arbiter Control Register Parking Mode Bits ......................................................... 7-8
7-2 PCI Bus Commands.................................................................................................... 7-10
7-3 Supported Combinations of AD[1:0].......................................................................... 7-12
7-4 PCI Configuration Space Header Summary ............................................................... 7-22
7-5 CONFIG_ADDR Register Fields ............................................................................... 7-24
7-6 Type 0 Configuration-Device Number to IDSEL Translation................................. 7-26
7-7 Special-Cycle Message Encodings ............................................................................. 7-28
7-8 Initialization Options for PCI Controller .................................................................... 7-33
8-1 DMA Register Summary .............................................................................................. 8-3
8-2 DMA Descriptor Summary......................................................................................... 8-12
8-3 DMR Field Descriptions-Offsets 0x100, 0x200 ...................................................... 8-16
8-4 DSR Field Descriptions-Offsets 0x104, 0x204........................................................ 8-19
8-5 CDAR Field Descriptions-Offsets 0x108, 0x208 .................................................... 8-20
8-6 SAR Field Description-Offsets 0x110, 0x210 ......................................................... 8-21
8-7 DAR Field Description-Offsets 0x118, 0x218......................................................... 8-21
8-8 BCR Field Descriptions-Offsets 0x120, 0x220........................................................ 8-22
8-9 NDAR Field Descriptions-Offsets 0x124, 0x224 .................................................... 8-23
9-1 Message Register Summary.......................................................................................... 9-2
9-2 Doorbell Register Summary ......................................................................................... 9-2
9-3 IMR and OMR Field Descriptions-Offsets 0x050-0x05C, 0x0_0050-0x0_005C.... 9-3
9-4 IDBR Field Descriptions-Offsets 0x068, 0x0_0068 .................................................. 9-4
9-5 ODBR Field Descriptions-Offsets 0x060, 0x0_0060 ................................................ 9-4
9-6 I O PCI Configuration Identification Register Settings ............................................... 9-5
2
9-7 I O Register Summary.................................................................................................. 9-5
2
9-8 Queue Starting Address ................................................................................................ 9-7
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