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Figure
Number
6-60
8-Bit ROM/Flash Interface-Cache-Line Read Timing............................................. 6-83
6-61
8-, 32-, or 64-Bit Flash Write Access Timing ............................................................ 6-84
6-62
PCI Read from ROM/Port X 64-Bit ........................................................................... 6-85
6-63
PCI Read from ROM/Port X 8-Bit (Part 1 of 4)......................................................... 6-86
6-63
Figure 6-63. (Continued) PCI Reads from ROM/Port X 8-Bit (Part 2 of 4) .............. 6-87
6-63
Figure 6-63. (Continued) PCI Reads from ROM/Port X 8-Bit (Part 3 of 4) .............. 6-88
6-63
Figure 6-63. (Continued) PCI Reads from ROM/Port X 8-Bit (Part 4 of 4) .............. 6-89
6-64
Port X Peripheral Interface Block Diagram................................................................ 6-90
6-65
Example of Port X Peripheral Connected to the MPC8240 ....................................... 6-91
6-66
Example of Port X Peripheral Connected to the MPC8240 ....................................... 6-92
6-67
Port X Example Read Access Timing ........................................................................ 6-92
6-68
Port X Example Write Access Timing........................................................................ 6-93
7-1
Internal Processor-DMA Arbitration for PCI Bus ........................................................ 7-5
7-2
PCI Arbitration Example .............................................................................................. 7-7
7-3
PCI Single-Beat Read Transaction ............................................................................. 7-15
7-4
PCI Burst Read Transaction........................................................................................ 7-16
7-5
PCI Single-Beat Write Transaction ............................................................................ 7-16
7-6
PCI Burst Write Transaction....................................................................................... 7-17
7-7
PCI Target-Initiated Terminations.............................................................................. 7-20
7-8
Standard PCI Configuration Header ........................................................................... 7-22
7-9
CONFIG_ADDR Register Format ............................................................................. 7-24
7-10
Type 0 Configuration Translation............................................................................... 7-25
7-11
PCI Parity Operation................................................................................................... 7-31
8-1
DMA Controller Block Diagram .................................................................................. 8-2
8-2
DMA Controller General Flow..................................................................................... 8-7
8-3
Chaining of DMA Descriptors in Memory................................................................. 8-13
8-4
DMA Mode Register (DMR)...................................................................................... 8-15
8-5
DMA Status Register (DSR)....................................................................................... 8-18
8-6
Current Descriptor Address Register (CDAR) ........................................................... 8-20
8-7
Source Address Register (SAR).................................................................................. 8-21
8-8
Destination Address Register (DAR).......................................................................... 8-21
8-9
Byte Count Register (BCR) ........................................................................................ 8-22
8-10
Next Descriptor Address Register (NDAR) ............................................................... 8-23
9-1
Message Registers (IMRs and OMRs) ......................................................................... 9-3
9-2
Inbound Doorbell Register (IDBR) .............................................................................. 9-3
9-3
Outbound Doorbell Register (ODBR) .......................................................................... 9-4
9-4
I
O Message Queue Example ....................................................................................... 9-7
2
9-5
Outbound Message Interrupt Status Register (OMISR) ............................................. 9-10
9-6
Outbound Message Interrupt Mask Register (OMIMR)............................................. 9-11
9-7
Inbound FIFO Queue Port Register (IFQPR) ............................................................. 9-11
9-8
Outbound FIFO Queue Port Register (OFQPR)......................................................... 9-12
9-9
Inbound Message Interrupt Status Register (IMISR) ................................................. 9-13
9-10
Inbound Message Interrupt Mask Register (IMIMR)................................................. 9-14
xxvi
ILLUSTRATIONS
Title
MPC8240 Integrated Processor User's Manual
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