Motorola MPC8240 User Manual page 11

Paragraph
Number
5.3.2.1 Calculating Effective Addresses............................................................... 5-18
5.3.2.2 PowerPC Instruction Set........................................................................... 5-18
5.3.2.3 MPC8240 Implementation-Specific Instruction Set................................. 5-20
5.4 Cache Implementation ...................................................................................... 5-20
5.4.1 PowerPC Cache Model................................................................................. 5-20
5.4.2 MPC8240 Implementation-Specific Cache Implementation........................ 5-21
5.4.2.1 Data Cache................................................................................................ 5-21
5.4.2.2 Instruction Cache ...................................................................................... 5-23
5.4.2.3 Cache Locking .......................................................................................... 5-23
5.4.2.3.1
5.4.2.3.2
5.4.3 Cache Coherency .......................................................................................... 5-24
5.4.3.1 CCU Responses to Processor Transactions .............................................. 5-24
5.4.3.2 Processor Responses to PCI-to-Memory Transactions............................. 5-25
5.5 Exception Model............................................................................................... 5-26
5.5.1 PowerPC Exception Model........................................................................... 5-26
5.5.2 MPC8240 Implementation-Specific Exception Model................................. 5-27
5.5.3 Exception Priorities....................................................................................... 5-30
5.6 Memory Management....................................................................................... 5-30
5.6.1 PowerPC MMU Model................................................................................. 5-30
5.6.2 MPC8240 Implementation-Specific MMU Features.................................... 5-31
5.7 Instruction Timing ............................................................................................ 5-32
5.8 Differences between the MPC8240 Core
and the PowerPC 603e Microprocessor........................................................ 5-34
6.1 Memory Interface Signal Summary.................................................................... 6-3
6.2 SDRAM Interface Operation .............................................................................. 6-6
6.2.1 Supported SDRAM Organizations ................................................................. 6-9
6.2.2 SDRAM Address Multiplexing .................................................................... 6-10
6.2.3 SDRAM Memory Data Interface.................................................................. 6-13
6.2.4 SDRAM Power-On Initialization ................................................................. 6-16
6.2.5 MPC8240 Interface Functionality for JEDEC SDRAMs ............................. 6-17
6.2.6 SDRAM Burst and Single-Beat Transactions .............................................. 6-18
6.2.7 SDRAM Page Mode ..................................................................................... 6-19
6.2.7.1 SDRAM Paging in Sleep Mode................................................................ 6-21
6.2.8 SDRAM Interface Timing ............................................................................ 6-21
6.2.8.1 SDRAM Mode-Set Command Timing ..................................................... 6-26
6.2.9 SDRAM Parity and RMW Parity ................................................................. 6-26
6.2.9.1 RMW Parity Latency Considerations ....................................................... 6-27
CONTENTS
Entire Cache Locking ........................................................................... 5-23
Way Locking ........................................................................................ 5-23
Chapter 6
MPC8240 Memory Interface
Contents
Title
Page
Number
xi