Inbound Post_Fifo Tail Pointer Register (Iptpr) - Motorola MPC8240 User Manual

31
Figure 9-13. Inbound Post_FIFO Head Pointer Register (IPHPR)
Table 9-17 shows the bit settings for the IPHPR.
Table 9-17. IPHPR Field Descriptions—Offset 0x0_0130
Reset
Bits Name
Value
31–20 QBA All 0s
19–2 IPHP All 0s
1–0 — 00

9.3.4.2.6 Inbound Post_FIFO Tail Pointer Register (IPTPR)

The processor picks up MFAs posted by PCI masters from the inbound post_list FIFO
pointed to by the inbound post_FIFO tail pointer register (IPTPR). The processor core is
responsible for updating the contents of IPTPR. Figure 9-14 shows the bits of the IPTPR.
31
Figure 9-14. Inbound Post_FIFO Tail Pointer Register (IPTPR)
Table 9-18 shows the bit settings for the IPTPR.
Table 9-18. IPTPR Field Descriptions—Offset 0x0_0138
Reset
Bits Name
Value
31–20 QBA All 0s
19–2 IPTP All 0s
1–0 — 00
QBA
20 19
R/W
R Queue base address. When read, this field returns the contents of QBAR[31–20].
RW Inbound post_FIFO head pointer. Maintains the local memory offset of the head
pointer of the inbound post _list FIFO.
R Reserved
QBA
20 19
R/W
R Queue base address. When read, this field returns the contents of QBAR[31–20].
RW Inbound post_FIFO tail pointer. The processor maintains the local memory offset
of the inbound post_list FIFO tail pointer in this field.
R Reserved
Chapter 9. Message Unit (with I
IPHP
Description
IPTP
Description
O)
2
I O Interface
2
Reserved
0 0
2 1 0
Reserved
0 0
2 1 0
9-17