Motorola MPC8240 User Manual page 172

Memory Control Configuration Registers
Table 4-38. Bit Settings for MCCR1—0xF0 (Continued)
Bits Name
20 BURST
19 MEMGO
18 SREN
17 RAM_TYPE
16 PCKEN
15–14 Bank 7 row
13–12 Bank 6 row
11–10 Bank 5 row
4-44
Reset
Value
0 Burst mode ROM timing enable
0 Indicates standard (nonburst) ROM access timing
1 Indicates burst-mode ROM access timing
0 RAM interface logic enable. Note that this bit must not be set until all other
memory configuration parameters have been appropriately configured by boot
code.
0 MPC8240 RAM interface logic disabled
1 MPC8240 RAM interface logic enabled
0 Self-refresh enable. Note that if self refresh is disabled, the system is
responsible for preserving the integrity of DRAM/EDO/SDRAM during sleep
mode.
0 Disables the DRAM/EDO/SDRAM self refresh during sleep mode
1 Enables the DRAM/EDO/SDRAM self refresh during sleep mode
1 RAM type
0 Indicates synchronous DRAM (SDRAM)
1 Indicates DRAM or EDO DRAM (depending on the setting for MCCR2[EDO])
Note that this bit must be cleared (selecting DRAM or SDRAM) before the in-line
or registered buffer mode bits in MCCR4 are set.
0 Memory interface parity checking/generation enable
0 Disables parity checking and parity generation for transactions to
DRAM/EDO/SDRAM memory. Note that this bit must be cleared for SDRAM
memory when operating in in-line buffer mode
(MCCR4[BUF_TYPE[0–1]] = 0b10) and in-line parity/ECC is enabled with
MCCR2[INLINE_RD_EN] = 1.
1 Enables parity checking and generation for all registered or flow-through mode
memory transactions to DRAM/EDO/SDRAM memory.
00 RAM bank 7 row address bit count. These bits indicate the number of row
address bits that are required by the RAM devices in bank 7.
For FPM/EDO DRAM configurations (RAM_TYPE = 1), the encoding is as
follows:
00 9 row bits
01 10 row bits
10 11 row bits
11 12 or 13 row bits
For SDRAM configurations (RAM_TYPE = 0), the encoding is as follows:
00 12 row bits by n column bits by 4 logical banks (12
11 row bits by n column bits by 4 logical banks (11
01 13 row bits by n column bits by 2 logical banks (13
12 row bits by n column bits by 2 logical banks (12
10 Reserved1111 row bits by n column bits by 2 logical banks (11
00 RAM bank 6 row address bit count. See the description for Bank 7 row (bits
15–14).
00 RAM bank 5 row address bit count. See the description for Bank 7 row (bits
15–14).
MPC8240 Integrated Processor User's Manual
Description
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