E.1.1.6 Link Register (Lr) - Motorola MPC8240 User Manual

Bit(s) Name
2 CA Carry. The carry bit (CA) is set during execution of the following instructions:
• Add carrying, subtract from carrying, add extended, and subtract from extended instructions
set CA if there is a carry out of the msb, and clear it otherwise.
• Shift right algebraic instructions set CA if any 1 bits have been shifted out of a negative
operand, and clear it otherwise.
The CA bit is not altered by compare instructions, nor by other instructions that cannot carry
(except shift right algebraic, mtspr to the XER, and mcrxr).
3–24 — Reserved
25–31 This field specifies the number of bytes to be transferred by a Load String Word Indexed (lswx) or
Store String Word Indexed (stswx) instruction.

E.1.1.6 Link Register (LR)

The format of LR is shown in Figure E-7.
0
E.1.1.7 Count Register (CTR)
The CTR is shown in Figure E-8.
0
The encoding for the BO field is shown in Table E-7.
BO
0000y Decrement the CTR, then branch if the decremented CTR ≠ 0 and the condition is FALSE.
0001y Decrement the CTR, then branch if the decremented CTR = 0 and the condition is FALSE.
001zy Branch if the condition is FALSE.
0100y Decrement the CTR, then branch if the decremented CTR ≠ 0 and the condition is TRUE.
0101y Decrement the CTR, then branch if the decremented CTR = 0 and the condition is TRUE.
011zy Branch if the condition is TRUE.
1z00y Decrement the CTR, then branch if the decremented CTR ≠ 0.
1z01y Decrement the CTR, then branch if the decremented CTR = 0.
Table E-6. XER Bit Definitions (Continued)
Branch Address
Figure E-7. Link Register (LR)
Figure E-8. Count Register (CTR)
Table E-7. BO Operand Encodings
Appendix E. Processor Core Register Summary
Description
CTR
Description
PowerPC Register Set
31
31
E-9