Example Of Port X Peripheral Connected To The Mpc8240 - Motorola MPC8240 User Manual

The ASRISE parameter controls when AS negates. For example, an ASRISE value of
0b0100 means that AS negates 4 clock cycles after it asserts. Setting ASRISE = 0
effectively disables AS and causes it to remain negated. At reset, both ASRISE and
ASFALL are initialized to 0. Example timing for Port X accesses is shown in Figure 6-67
and Figure 6-68.
Due to restrictions in the ROM and Flash controllers, the ASFALL and ASRISE parameters
should be programmed as ASRISE + ASFALL ≤ ROMFAL + 7 if the ROM interface is
programmed to support 8-bit data bus mode for RCS0, (DBUS_SIZE = x1). Otherwise
ASFALL and ASRISE should be programmed as ASRISE + ASFALL ≤ ROMFAL + 4.
Note that AS may not negate between back-to-back Port X transfers if ASFALL is set to
0x0, and ASRISE is set to the maximum allowed value.
The ROM and Flash controllers are capable of multiple-beat read operations (that is,
multiple data tenures for one address tenure). Note, however, that if a Port X device is
accessed with a multiple-beat read operation, AS asserts and negates only once and not
multiple times after RCS[0 or 1] asserts.
The following minimum negation times apply for RCS[0–1] in between Port X
transactions:
• 5 clocks (8-bit data bus reads and all writes); typically greater due to processor and
CCU activity
• 2 clocks (32- or 64-bit data bus reads); typically greater due to processor and CCU
activity
MPC8240
MDH[0:31]
MDL[0:31]
PAR[0:7]
SDMA[12:0]
BUFFERS
RCS0
AS
RCS1
WE
Figure 6-65. Example of Port X Peripheral Connected to the MPC8240
Data path SDRAM or DRAM Array
Parity path SDRAM or DRAM Array
Address path SDRAM or DRAM Array
Address path Flash or ROM
ROM Chip Select 0 to ROM
Chapter 6. MPC8240 Memory Interface
ROM/Flash Interface Operation
D[0:63]
A0:A18
Port X
AS
I/O Device (s)
CE
WE
6-91