Fpm Or Edo Dram Initialization - Motorola MPC8240 User Manual

The data path between the internal processor bus to the external memory bus in
flow-through mode is shown in Figure 6-34. The flow-through mode is the default data bus
buffering mode for the MPC8240.
Note that in-line ECC is not available with FPM or EDO DRAM.
Processor data from DRAM
Processor data to DRAM
Output enable
Figure 6-34. FPM-EDO Flow-through Memory Interface

6.3.4 FPM or EDO DRAM Initialization

At system reset, the main memory is inactive. When the reset signals (HRST_CPU and
HRST_CTRL) are negated, the MEMGO bit is cleared to zero (0) which turns off the
memory controller. The processor 5core starts fetching boot code from ROM (local or PCI).
For systems containing FPM or EDO DRAM, the boot code must set the MPC8240
configuration bit RAMTYP = 1.
Additionally, all other MPC8240 configuration registers relevant to DRAM must be
initialized. Table 6-21 shows the register fields in the memory interface configuration
registers (MICRs) and the memory control configuration registers (MCCRs).
Table 6-21. Memory Interface Configuration Register Fields
Register Field
RAM_TYPE
Memory Bank
Start and End Addresses
Memory Bank Enables
Row Address Bits For Each Bank
PCKEN
SREN
REFINT
RP1
RCD2
CAS3
CP4
CAS5
RAS6P
RMW_PAR
Description
SDRAM, FPM, or EDO DRAM
Parity check enable
Self refresh enable
Interval between refreshes
RAS precharge interval
RAS to CAS delay
CAS assertion interval for first data beat
CAS precharge interval
CAS assertion interval for page mode data beats
RAS assertion interval for CBR refresh
Read modify write parity
Chapter 6. MPC8240 Memory Interface
FPM or EDO DRAM Interface Operation
signals
DRAM data path
Configuration
Register (and offset)
MCCR1 @ <F0>
MICR @ <80>–<9C>
MICR @ <A0>
MCCR1 @ <F0>
MCCR1 @ <F0>
MCCR1 @ <F0>
MCCR2 @ <F4>
MCCR3 @ <F8>
MCCR3 @ <F8>
MCCR3 @ <F8>
MCCR3 @ <F8>
MCCR3 @ <F8>
MCCR3 @ <F8>
MCCR2 @ <F4>
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