Outbound Post_List Fifo - Motorola MPC8240 User Manual

I O Interface
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9.3.3.2.2 Outbound Post_List FIFO

The outbound post_list FIFO holds MFAs that are posted from the processor core to remote
processors. The processor core places messages in the outbound post_list FIFO by writing
the MFA to OPHPR. This software must then increment the value in OPHPR.
When the FIFO is not empty (head and tail pointers are not equal), the outbound post_list
queue interrupt bit in the outbound message interrupt status register (OMISR[OPQI]) is set.
Additionally, the external MPC8240 PCI interrupt signal (INTA) is asserted (if it is not
masked). When the head and tail pointers are equal, OMISR[OPQI] is cleared. The
outbound post_list queue interrupt can be masked using the outbound message interrupt
mask register (OMIMR).
An external PCI master reads the outbound FIFO queue port register (OFQPR) to cause the
MPC8240's I O unit to read the MFA from local memory pointed to by the OPTPR. The
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I O unit then automatically increments the value in OPTPR.
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When the FIFO is empty (head and tail pointers are equal), the unit returns 0xFFFF_FFFF.
9.3.4 I O Register Descriptions
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The following sections provide detailed descriptions of the I O registers and some of the
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bits that control the generic message and doorbell register interface in these registers. See
Chapter 11, "Embedded Programmable Interrupt Controller (EPIC) Unit," for more
information on the interrupt mechanisms of the MPC8240.
9.3.4.1 PCI-Accessible I O Registers
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The OMISR, OMIMR, IFQPR, and OFQPR registers are used by PCI masters to access the
MPC8240 I O unit. The processor core cannot access any of these registers.
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9.3.4.1.1 Outbound Message Interrupt Status Register (OMISR)
The OMISR contains the interrupt status of the I O, doorbell register, and outbound
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message register events that cause the assertion of INTA. These events are generated by
blocks in the MPC8240 and the assertion of INTA signals an interrupt to the PCI bus on
behalf of these blocks.
Writing a 1 to a set bit in OMISR clears the bit (except for read-only bits). Software
attempting to determine the source of the interrupts should always perform a logical AND
between the OMISR bits and their corresponding mask bits in the OMIMR.
Chapter 9. Message Unit (with I O) 9-9
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