Internal Arbitration - Motorola MPC8240 User Manual

Internal Arbitration

If the snoop on the peripheral logic bus hits modified data in the L1 cache, the snoop
copyback data is merged with the data in the appropriate PCMWB, and the full cache line
is sent to memory. For the PCI memory-write-and-invalidate command, a snoop hit in the
L1 cache invalidates any modified cache line without requiring a copyback.
Note that a PCI transaction that hits in either of the PCMWBs does not require a snoop on
the peripheral logic bus. However, if a PCI write address hits in a
PCI-read-from-local-memory buffer (PCMRB), the CCU invalidates the PCMRB and
snoops the address on the peripheral logic bus.
When the PCI write is complete and the snooping is resolved, the data is flushed to memory
at the first available opportunity.
For a stream of single-beat writes, the data for the first transaction is latched in the first
buffer and the CCU initiates the snoop transaction on the peripheral logic bus. For
subsequent single-beat writes, gathering is possible if the incoming write is to the same
cache line as the previously latched data. Gathering in the first buffer can continue until the
buffer is scheduled to be flushed, or until a write occurs to a different address. If there is
valid data in both buffers, further gathering is not supported until one of the buffers has been
flushed.
12.2 Internal Arbitration
The MPC8240 performs arbitration internally for the internal shared processor/memory
data bus. Note that all processor-to-PCI transactions are performed strictly in-order with
respect to the MPC8240. Also, all snoops for PCI accesses to local memory are performed
in order (if snooping is enabled).
12.2.1 Arbitration Between PCI and DMA Accesses to Local
Memory
For the purposes of the CCU, the two DMA channels of the MPC8240 DMA controller
function as PCI devices on the MPC8240 as shown in Figure 12-5.
DMA 0 access to local memory
PCI device access to local memory
Internal
Arbitration Logic
DMA 1 access to local memory
External PCI access to local memory
Figure 12-5. PCI/DMA Arbitration for Local Memory Accesses
Chapter 12. Central Control Unit 12-9