Motorola MPC8240 User Manual page 507

Table 16-3. Watchpoint Control Trigger Register Bit Field Definitions (Continued)
Bits Name Reset Value
20–16 TT[0:4] 0b0_0000
15 TBST_ 0
14–12 TSIZ[0:2] 0b000
11 GBL_ 0
10 CI_ 0
9 WT_ 0
8–7 TC[0:1] 0b00
6 AACK_ 0
5 ARTRY_ 0
4 DBG_ 0
3 TA_ 0
2 TEA_ 0
1 INT_ 0
0 MCP_ 0
Figure 16-4 and Figure 16-5 show the format of the watchpoint #1 and watchpoint #2
address trigger registers (WP1_ADDR_TRIG and WP2_ADDR_TRIG). The format is
identical, but they are shown separately to show the offsets.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Figure 16-4. Watchpoint #1 Address Trigger Register (WP1_ADDR_TRIG)—
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Figure 16-5. Watchpoint #2 Address Trigger Register (WP2_ADDR_TRIG)—
R/W
R/W Trigger match condition for TT[0:4] setting on peripheral logic bus
R/W 0 Trigger if TBST asserted on peripheral logic bus
1 Trigger if TBST negated
R/W Trigger match condition for TSIZ[0:2] on peripheral logic bus
R/W 0 Trigger if GBL asserted on peripheral logic bus
1 Trigger if GBL negated
R/W 0 Trigger if CI asserted on peripheral logic bus
1 Trigger if CI negated
R/W 0 Trigger if WT asserted on peripheral logic bus
1 Trigger if WT negated
RW Trigger match condition for TC[0:1] on peripheral logic bus
R/W 0 Trigger if AACK asserted on peripheral logic bus
1 Trigger if AACK negated
R/W 0 Trigger if ARTRY asserted on peripheral logic bus
1 Trigger if ARTRY negated
R/W 0 Trigger if DBG asserted on peripheral logic bus
1 Trigger if DBG negated
R/W 0 Trigger if TA asserted on peripheral logic bus
1 Trigger if TA negated
R/W 0 Trigger if TEA asserted on peripheral logic bus
1 Trigger if TEA negated
R/W 0 Trigger if INT asserted on peripheral logic bus
1 Trigger if INT negated
R/W 0 Trigger if MCP asserted on peripheral logic bus
1 Trigger if MCP negated
A[31:0]
Offsets 0xF_F01C, 0xF1C
A[31:0]
Offsets 0xF_F034, 0xF34
Chapter 16. Programmable I/O and Watchpoint
Watchpoint Registers
Description
9 8 7 6 5 4
9 8 7 6 5 4
3 2 1 0
3 2 1 0
16-5