Programmable I/O Signals With Watchpoint; Debug Features - Motorola MPC8240 User Manual

.
Table 1-2. Peripheral Logic Power Modes Summary
PM
Functioning Units
Mode
Full All units active
power
Doze PCI address decoding and bus arbiter
System RAM refreshing
Processor bus request and NMI monitoring
EPIC unit
2
I C unit
PLL
Nap PCI address decoding and bus arbiter
System RAM refreshing
Processor bus request and NMI monitoring
EPIC unit
2
I C unit
PLL
Sleep PCI bus arbiter
System RAM refreshing (can be disabled)
Processor bus request and NMI monitoring
EPIC unit
2
I C unit
PLL (can be disabled)
1
Programmable option based on value of PICR1[MCP_EN] = 1
2
A PCI access to memory in nap mode does not cause QACK to negate; consequently, it does not wake up the
processor core, and the processor core won't snoop this access. After servicing the PCI access, the peripheral
logic automatically returns to the nap mode.

1.6 Programmable I/O Signals with Watchpoint

The MPC8240 programmable I/O facility allows the system designer to monitor the
peripheral logic bus. Up to two watchpoints and their respective 4-bit countdown values can
be programmed. When the programmed threshold of the selected watchpoint is reached, an
external trigger signal is generated.

1.7 Debug Features

The MPC8240 includes the following debug features:
• Memory attribute and PCI attribute signals
• Debug address signals
• MIV signal: Marks valid address and data bus cycles on the memory bus.
• Error injection/capture on data path
• IEEE 1149.1 (JTAG)/test interface
Programmable I/O Signals with Watchpoint
Activation Method
—
Controlled by software
(write to PMCR1)
Controlled by software
(write to PMCR1) and
processor core in nap or
sleep mode (QREQ
asserted)
Controlled by software
(write to PMCR1) and
processor core in nap or
sleep mode (QREQ
asserted)
Chapter 1. Overview
Full-Power Wake Up
Method
—
PCI access to memory
Processor bus request
1
Assertion of NMI
Interrupt to EPIC
Hard Reset
2
PCI access to memory
Processor bus request
1
Assertion of NMI
Interrupt to EPIC
Hard Reset
Processor bus request
1
Assertion of NMI
Interrupt to EPIC
Hard Reset
1-19