B.3 Big-Endian Mode - Motorola MPC8240 User Manual

Big-Endian Mode
the PowerPC core. The LE bit specifies the endian mode for normal core operation and ILE
specifies the mode to be used when an exception handler is invoked. That is, when an
exception occurs, the ILE bit (as set for the interrupted process) is copied into MSR[LE] to
select the endian mode for the context established by the exception. The LE and ILE bits
control a 3-bit address modifier in the processor core.
To convert from PowerPC little-endian to true little-endian byte ordering, all the byte lanes
must be reversed (MSB to LSB, and so on) and the addresses must be unmunged external
to the processor core. When configured for little-endian mode, the MPC8240 unmunges the
address and reverses the byte lanes between the PCI bus and local memory in the central
control unit (CCU). This means that the data in local memory is stored using PowerPC
little-endian byte ordering, but data on the PCI bus is in true little-endian byte order. The
PICR1[LE_MODE] parameter controls a 3-bit address modifier and byte lane swapper in
the CCU.
Note that the processor core and the CCU should be set for the same endian mode before
accessing devices on the PCI bus.

B.3 Big-Endian Mode

When the processor core is operating in big-endian mode, no address modification is
performed by the processor. In big-endian mode, the MPC8240 maintains the big-endian
byte ordering on the PCI bus during the data phase(s) of PCI transactions. The byte lane
translation for big-endian mode is shown in Table B-1. Note that the bit ordering on the PCI
bus remains unchanged (that is, AD31 is still the msb of the byte in byte lane 3 and AD0 is
still the lsb of the byte in byte lane 0).
Table B-1. Byte Lane Translation in Big-Endian Mode
Processor
Byte Lane
0
1
2
3
4
5
6
7
B-2
Processor Data Bus
Signals
DH[0–7]
DH[8–15]
DH[16–23]
DH[24–31]
DL[0–7]
DL[8–15]
DL[16–23]
DL[24–31]
MPC8240 Integrated Processor User's Manual
PCI Address/Data Bus
PCI Byte Lane Signals During PCI Data
0
1
2 AD[23–16]
3 AD[31–24]
0
1
2 AD[23–16]
3 AD[31–24]
Phase
AD[7–0]
AD[15–8]
AD[7–0]
AD[15–8]