Processor Sleep Mode - Motorola MPC8240 User Manual

Processor Core Power Management

14.2.3.5 Processor Sleep Mode

Sleep mode consumes the least amount of power of the four modes since all functional units
are disabled. To conserve the maximum amount of power, the processor PLL and the
internal sys_logic_clk signals can be disabled to the processor. Due to the fully static design
of the MPC8240, internal processor state is preserved when no internal clock is present.
Because the time base and decrementer are disabled while the processor is in sleep mode,
the time base contents must be updated from an external time base following sleep mode if
accurate time-of-day maintenance is required.
As in nap mode, the peripheral logic block delays the processor from entering into sleep
mode until all the internal buffers are flushed and there is no outstanding transaction. When
the peripheral logic block has ensured that snooping is no longer necessary, it allows the
processor core to enter the sleep mode and it asserts the QACK output signal for the
duration of the sleep mode period.
Sleep mode is characterized by the following features:
• All processor functional units disabled (including bus snooping and time base)
• All nonessential input receivers disabled
• Internal clock regenerators disabled
• Processor PLL and the internal sys_logic_clk signal can be disabled.
To enter sleep mode the following conditions must occur:
• Set sleep bit (HID0[10] = 1).
• Processor asserts internal request for nap or sleep mode to the peripheral logic.
• Peripheral logic must be programmed for nap or sleep mode.
• MPC8240 asserts quiesce acknowledge (QACK) output signal after flushing the
internal buffers of peripheral logic block.
• Processor core enters sleep mode after several processor clocks. (Peripheral logic
also enters the nap or sleep mode.)
To return to full-power mode the following conditions must occur:
• Internal int or mcp signals asserted or QACK negated by the peripheral logic block,
NMI asserted, or SMI asserted
• Hard reset or soft reset
14.2.4 Power Management Software Considerations
Because the processor core is a dual-issue processor with out-of-order execution capability,
care must be taken in how the processor power management modes are entered.
Furthermore, nap and sleep modes require all outstanding bus operations to be completed
14-6 MPC8240 Integrated Processor User's Manual