Data Transfer - Motorola MPC8240 User Manual

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I C Protocol

10.2.3 Data Transfer

When successful slave addressing is achieved (and SCL returns to zero), the data transfer
can proceed on a byte-to-byte basis in the direction specified by the R/W bit sent by the
calling master.
Each data byte is eight bits long. Data bits can be changed only while the SCL signal is low
and must be held stable while the SCL signal is high, as shown in Figure 10-2. There is one
clock pulse on SCL for each data bit, and the most significant bit (msb) is transmitted first.
Each byte of data must be followed by an acknowledge bit, which is signalled from the
receiving device by pulling the SDA line low at the 9th clock. Therefore, one complete data
byte transfer takes nine clock pulses. Several bytes can be transferred during a data transfer
session.
If the slave receiver does not acknowledge the master, the SDA line must be left high by the
slave. The master can then generate a stop condition to abort the data transfer or a START
condition (repeated START) to begin a new calling.
If the master receiver does not acknowledge the slave transmitter after a byte of
transmission, the slave interprets that the end-of-data has been reached. Then the slave
releases the SDA line for the master to generate a STOP or a START condition.
10.2.4 Repeated START Condition
As shown in Figure 10-2, a repeated START condition is a START condition generated
without a STOP condition to terminate the previous transfer. The master uses this method
to communicate with another slave or with the same slave in a different mode
(transmit/receive mode) without releasing the bus.
10.2.5 STOP Condition
The master can terminate the transfer by generating a STOP condition to free the bus. A
STOP condition is defined as a low-to-high transition of the SDA signal while SCL is high.
For more information, see Figure 10-2. Note that a master can generate a STOP even if the
slave has transmitted an acknowledge bit, at which point the slave must release the bus.
As described in Section 10.2.4, "Repeated START Condition," the master can generate a
START condition followed by a calling address without generating a STOP condition for
the previous transfer. This is called a repeated START condition.
10.2.6 Arbitration Procedure
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The I C interface is a true multiple master bus that allows more than one master device to
be connected on it. If two or more masters try to control the bus simultaneously, each master
(including the MPC8240) has a clock synchronization procedure that determines the bus
clock—the low period is equal to the longest clock low period, and the high is equal to the
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Chapter 10. I C Interface 10-5