Error Handling Block Diagram - Motorola MPC8240 User Manual

Overview

13.1.1 Error Handling Block Diagram

Figure 13-1 provides the internal error management block diagram.
HRST_CPU
HRST_CRTL
Figure 13-1. Internal Error Management Block Diagram
13.1.2 Priority of Externally Generated Errors and
Exceptions
Many of the errors detected in the MPC8240 cause exceptions to be taken by the processor
core. Table 13-1 describes the relative error priorities.The processor exception generated by
each of these conditions is described in Section 5.5, "Exception Model."
Priority Exception
0 Hard reset
1 Machine check
2 Machine check
3 Machine check
13-2
SMI
Processor Core
Peripheral Logic Interface
NMI
Error
Handling
PCI Interface
Table 13-1. MPC8240 Error Priorities
Hard reset (required on power-on); HRST_CRTL and HRST_CPU asserted (must
always be asserted together)
Processor transaction error or Flash write error
PCI address parity error (SERR) or PCI data parity error (PERR) when the
MPC8240 is acting as the PCI target
Memory select error, memory data read parity error, memory refresh overflow, or
ECC error
MPC8240 Integrated Processor User's Manual
Memory
Message
Unit
Parity/ECC
Check
PERR SERR
Cause
MCP