Target Ready (Trdy)—Input - Motorola MPC8240 User Manual

Detailed Signal Descriptions
2.2.1.10.2 Target Ready (TRDY)—Input
Following is the state meaning for TRDY as an input signal.
State Meaning
2.2.1.11 Parity Error (PERR)
The PCI parity error (PERR) signal is both an input and output signal on the MPC8240. See
Section 13.2.3.2, "Parity Error (PERR)," and Section 4.8.2, "Error Enabling and Detection
Registers," for more information on how the MPC8240 is set up to report parity errors. The
PCI initiator drives PERR on read operations; the PCI target drives PERR on write
operations.
2.2.1.11.1 Parity Error (PERR)—Output
Following is the state meaning for PERR as an output signal.
State Meaning
2.2.1.11.2 Parity Error (PERR)—Input
Following is the state meaning for PERR as an input signal.
State Meaning
2.2.1.12 System Error (SERR)
The PCI system error (SERR) signal is both an input and output signal on the MPC8240. It
is an open-drain signal and can be driven by multiple devices on the PCI bus. Refer to
Section 13.2.3.1, "System Error (SERR)," and Section 4.8.2, "Error Enabling and
Detection Registers," for more information on how the MPC8240 drives and reports system
errors.
2-14
Asserted—Indicates another PCI target is able to complete the
current data phase of a transaction. If the MPC8240 is the initiator of
the transaction, it latches the data (on a read) or cycles the data on a
write.
Negated—Indicates a wait cycle needed by a target. If the MPC8240
is the initiator of the transaction, it waits to latch the data (on a read)
or continues to drive the data (on a write).
Asserted—Indicates that the MPC8240, acting as a PCI agent,
detected a data parity error.
Negated—Indicates no error.
Asserted—Indicates that another PCI agent detected a data parity
error while the MPC8240 was sourcing data (the MPC8240 was
acting as the PCI initiator during a write, or was acting as the PCI
target during a read).
Negated—Indicates no error.
MPC8240 Integrated Processor User's Manual