Configuration Register Summary; Processor-Accessible Configuration Registers - Motorola MPC8240 User Manual

Example: Map A configuration sequence, 4-byte data write to register at address offset
0xA8, using byte-swapped values in the processor registers
Initial values:r0 contains 0xA800_0080
r1 contains 0x8000_0CF8
r2 contains 0xDDCC_BBAA
Register at 0xA8 contains 0xFFFF_FFFF (AB to A8)
Code sequence: stw
sync
stw
sync
Results:Address 0x8000_0CF8 contains 0x8000_00A8 (MSB to LSB)
Register at 0xA8 contains 0xAABB_CCDD (AB to A8)
4.1.3 Configuration Register Summary
The following sections summarize the addresses and attributes of the configuration
registers accessible by both the processor and the PCI interface.
4.1.3.1 Processor-Accessible Configuration Registers
Table 4-2 describes the configuration registers that are accessible by the processor core. Not
all registers are shown in this document. Note that any configuration addresses not defined
in Table 4-2 are reserved.
Table 4-2. MPC8240 Configuration Registers Accessible
Address
Offset
0x00 Vendor ID = 0x1057 (not shown)
0x02 Device ID = 0x0003 (not shown)
0x04 PCI command register
0x06 PCI status register
0x08 Revision ID (not shown)
0x09 Standard programming interface
0x0A Subclass code (not shown)
0x0B Class code
0x0C Cache line size
0x0D Latency timer
r0,0(r1)
r2,4(r1)
from the Processor Core
Register
2 bytes
2 bytes
2 bytes
2 bytes
1 byte
1 byte
1 byte
1 byte
1 byte
1 byte
Chapter 4. Configuration Registers
Configuration Register Access
Program
Size Access
Size (Bytes)
2 Read
2 Read
2 Read/Write
2 Read/Bit Reset
1 Read
1 Read
1 Read
1 Read
1 Read/Write
1 Read/Write
Access Reset Value
0x1057
0x0003
mode-dependent
0x0004 host
0x0000 agent
0x00A0
0xnn
mode-dependent
0x00 host
0x01 agent
0x00
mode-dependent
0x06 host
0x0E agent
0x00
0x00
4-5