E.3.3 Hardware Implementation-Dependent Register 2 (Hid2) - Motorola MPC8240 User Manual

MPC8240-Specific Registers
E.3.3 Hardware Implementation-Dependent Register 2
(HID2)
The processor core implements an additional hardware implementation-dependent register
as shown in Figure E-29, not described in the MPC603e User's Manual. HID2 can be
accessed with mfspr using SPR1011.
0000 0000 0000 0000
0
Figure E-29. Hardware Implementation-Dependent Register 2 (HID2)
Table E-23 describes the HID2 fields.
Bits Name
0–15 — Reserved
16–18 IWLCK Instruction cache way lock—Useful for locking blocks of instructions into the instruction cache for
time-critical applications where deterministic behavior is required. Refer to Section 5.4.2.3,
"Cache Locking," for more information.
19–23 — Reserved
24–26 DWLCK Data cache way lock—Useful for locking blocks of data into the data cache for time-critical
applications where deterministic behavior is required. Refer to Section 5.4.2.3, "Cache Locking,"
for more information.
27–31 — Reserved
E-28
Table E-23. HID2 Field Descriptions
MPC8240 Integrated Processor User's Manual
0 0000
IWLCK
15 16 18 19
Function
0 0000
DWLCK
23 24 26 27 31