Initialization Sequence - Motorola MPC8240 User Manual

Programming Guidelines

10.4.1 Initialization Sequence

A hard reset initializes all the I
initialization sequence must be used before the I
1. If the processor's memory management unit (MMU) is enabled, all I
must be located in a cache-inhibited area.
2. Program the embedded utilities memory block; see Section 3.4, "Embedded
Utilities Memory Block (EUMB)."
3. Update I2CFDR[FDR] and select the required division ratio to obtain the SCL
frequency from the local memory clock (SDRAM_CLK).
4. Update the I2CADR to define the slave address for this device.
5. Modify I2CCR to select master/slave mode, transmit/receive mode, and
interrupt-enable or disable.
6. Set the I2CCR[MEN] to enable the I
10.4.2 Generation of START
After initialization, the following sequence can be used to generate START:
1. If the MPC8240 is connected to a multimaster I
I2CSR[MBB] to check whether the serial bus is free (I2CSR[MBB] = 0) before
switching to master mode.
2. Select master mode (set I2CCR[MSTA]) to transmit serial data.
3. Write the slave address being called into the data register (I2CDR). The data written
to I2CDR[7–1] comprises the slave calling address. I2CCR[MTX] indicates the
direction of transfer (transmit/receive) required from the slave.
4. Set I2CCR[MTX] for the address cycle.
The above scenario assumes the I
I2CSR[MIF] = 1 at any time, the I
interrupt. See Section 10.4.8, "Interrupt Service Routine Flowchart."
10.4.3 Post-Transfer Software Response
Transmission or reception of a byte automatically sets the data transferring bit
(I2CSR[MCF]), which indicates that one byte has been transferred. The I
(I2CSR[MIF]) is also set; an interrupt is generated to the processor if the interrupt function
is enabled during the initialization sequence (I2CCR[MIEN] = 1). In the interrupt handler,
software must do the following:
• Clear I2CSR[MIF]
• Read the contents of the I
I2CDR in transmit mode. Note that this causes I2CSR[MCF] to be cleared. See
Section 10.4.8, "Interrupt Service Routine Flowchart."
10-14
2
C registers to their default states. The following
2
C interface.
2
C interrupt bit (I2CSR[MIF]) is cleared. If
2
C interrupt handler should immediately handle the
2
C data register (I2CDR) in receive mode or write to
MPC8240 Integrated Processor User's Manual
2
C unit:
2
C system, test the state of
2
C registers
2
C interrupt bit