Memory Space Addressing - Motorola MPC8240 User Manual

PCI Bus Protocol

7.3.3.1 Memory Space Addressing

For memory accesses, PCI defines two types of burst ordering controlled by the two
low-order bits of the address—linear incrementing (AD[1:0] = 0b00) and cache wrap mode
(AD[1:0] = 0b10). The other two AD[1:0] possibilities (0b01 and 0b11) are reserved.
As an initiator, the MPC8240 always encodes AD[1:0] = 0b00 for PCI memory space
accesses. As a target, the MPC8240 executes a target disconnect after the first data phase
completes if AD[1:0] = 0b01 or AD[1:0] = 0b11 during the address phase of a local
memory access. See Section 7.4.3.2, "Target-Initiated Termination," for more information
on target disconnect conditions.
Table 7-3. Supported Combinations of AD[1:0]
AD[1:0]
00
01
10
11
For linear incrementing mode, the memory address is encoded/decoded using AD[31:2].
Thereafter, the address is incremented by 4 bytes after each data phase completes until the
transaction is terminated or completed (a 4-byte data width per data phase is implied). Note
that the two low-order bits on the address bus are included in all parity calculations.
For cache wrap mode (AD[1:0] = 0b10) reads, the critical memory address is decoded
using AD[31:2]. The address is incremented by 4 bytes after each data phase completes
until the end of the cache line is reached. For cache-wrap reads, the address wraps to the
beginning of the current cache line and continues incrementing until the entire cache line
(32 bytes) is read. The MPC8240 does not support cache-wrap write operations and
executes a target disconnect after the first data phase completes for writes with
AD[1:0] = 0b10. Again, note that the two low-order bits on the address bus are included in
all parity calculations.
7.3.3.2 I/O Space Addressing
For PCI I/O accesses, all 32 address signals (AD[31:0]) are used to provide a byte address.
After a target has claimed an I/O access, it must determine if it can complete the entire
access as indicated by the byte enable signals. If all the selected bytes are not in the address
range of the target, the entire access cannot complete. In this case, the target does not
transfer any data and terminates the transaction with a target-abort error. See
Section 7.4.3.2, "Target-Initiated Termination," for more information.
7-12
MPC8240 as Target
Read
Linear √
reserved TD
Cache wrap √
reserved TD
MPC8240 Integrated Processor User's Manual
MPC8240 as Initiator
Write Read
√ √
TD —
TD —
TD —
Write
√
—
—
—