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PowerPC Processor Core Features
5.2.2 Instruction Queue and Dispatch Unit
The instruction queue (IQ), shown in Figure 5-1, holds as many as six instructions and
loads up to two instructions from the instruction unit during a single cycle. The instruction
fetch unit continuously loads as many instructions as the space in the IQ allows.
Instructions are dispatched to their respective execution units from the dispatch unit at a
maximum rate of two instructions per cycle. Reservation stations at the IU, FPU, LSU, and
SRU facilitate instruction dispatch to those units. The dispatch unit checks for source and
destination register dependencies, determines dispatch serializations, and inhibits
subsequent instruction dispatching as required. Section 5.7, "Instruction Timing,"
describes instruction dispatch in detail.
5.2.3 Branch Processing Unit (BPU)
The BPU receives branch instructions from the fetch unit and performs CR lookahead
operations on conditional branches to resolve them early, achieving the effect of a
zero-cycle branch in many cases.
The BPU uses a bit in the instruction encoding to predict the direction of the conditional
branch. Therefore, when an unresolved conditional branch instruction is encountered,
instructions are fetched from the predicted target stream until the conditional branch is
resolved.
The BPU contains an adder to compute branch target addresses and three user-control
registers—the link register (LR), the count register (CTR), and the condition register (CR).
The BPU calculates the return pointer for subroutine calls and saves it into the LR for
certain types of branch instructions. The LR also contains the branch target address for the
Branch Conditional to Link Register (bclrx) instruction. The CTR contains the branch
target address for the Branch Conditional to Count Register (bcctrx) instruction. The
contents of the LR and CTR can be copied to or from any GPR. Because the BPU uses
dedicated registers rather than GPRs or FPRs, execution of branch instructions is largely
independent from execution of other instructions.
5.2.4 Independent Execution Units
The PowerPC architecture's support for independent execution units allows
implementation of processors with out-of-order instruction execution. For example,
because branch instructions do not depend on GPRs or FPRs, branches can often be
resolved early, eliminating stalls caused by taken branches.
In addition to the BPU, the processor core provides four other execution units and a
completion unit, which are described in the following sections.
5-6
MPC8240 Integrated Processor User's Manual
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