Messaging Unit Control Register (Mucr) - Motorola MPC8240 User Manual

I O Interface
2
Figure 9-18 shows the bits of the OPTPR.
31
Figure 9-18. Outbound Post_FIFO Tail Pointer Register (OPTPR)
Table 9-22 shows the bit settings for the OPTPR.
Table 9-22. OPTPR Field Descriptions— Offset 0x0_0158
Reset
Bits Name
Value
31–20 QBA All 0s
19–2 OPTP All 0s
1–0 — 00

9.3.4.2.11 Messaging Unit Control Register (MUCR)

The MUCR allows software to enable and set up the size of the inbound and outbound
FIFOs. Figure 9-19 shows the bits of the MUCR.
0 0 0 0_0 0 0 0_0 0 0 0_0 0 0 0_0 0 0 0_0 0 0 0_0 0
31
Figure 9-19. Messaging Unit Control Register (MUCR)
Table 9-23 shows the bit settings for the MUCR.
Table 9-23. MUCR Field Descriptions— Offset 0x0_0164
Reset
Bits Name
Value
31–6 — All 0s
5–1 CQS 0b0_0001
0 CQE 0
9-20
QBA
20 19
R/W
R Queue base address. When read, this field returns the contents of QBAR[31–20].
RW Outbound post_FIFO tail pointer. Maintains the local memory offset of the tail
pointer of the outbound post_list FIFO.
R Reserved
R/W
R Reserved
RW Circular queue size
0b0_0001: 4K entries (16 Kbytes)
0b0_0010: 8K entries (32 Kbytes)
0b0_0100: 16K entries (64 Kbytes)
0b0_1000: 32K entries (128 Kbytes)
0b1_0000: 64K entries (256 Kbytes)
RW Circular queue enable
0 PCI writes to IFQPR and OFQPR are ignored and reads return
0xFFFF_FFFF.
1 Allows PCI masters to access the inbound and outbound queue ports (IFQPR
and OFQPR). Usually, this bit is set only after software has initialized all
pointers and configuration registers.
MPC8240 Integrated Processor User's Manual
OPTP
Description
6 5
Description
Reserved
0 0
2 1 0
Reserved
CQE
CQS
1 0