Table 4-21. Bit Settings for Extended Memory Starting Address Registers 1 and 2
Bits
Name
31–26
—
25–24
Extended starting address 3
23–18
—
17–16
Extended starting address 2
15–10
—
9–8
Extended starting address 1
7–2
—
1–0
Extended starting address 0
31–26
—
25–24
Extended starting address 7
23–18
—
17–16
Extended starting address 6
15–10
—
9–8
Extended starting address 5
7–2
—
1–0
Extended starting address 4
Figure 4-11, Figure 4-12, and Table 4-22 depict the memory ending address register 1 and
2 bit settings.
Ending Address Bank 3 Ending Address Bank 2 Ending Address Bank 1 Ending Address Bank 0
31
Figure 4-11. Memory Ending Address Register 1—0x90
Ending Address Bank 7 Ending Address Bank 6 Ending Address Bank 5 Ending Address Bank 4
31
Figure 4-12. Memory Ending Address Register 2—0x94
Table 4-22. Bit Settings for Memory Ending Address Registers 1 and 2
Bits
31–24
Ending address bank 3
23–16
Ending address bank 2
15–8
Ending address bank 1
7–0
Ending address bank 0
Reset Value
All 0s
0b00
All 0s
0b00
All 0s
0b00
All 0s
0b00
All 0s
0b00
All 0s
0b00
All 0s
0b00
All 0s
0b00
24 23
24 23
Name
Reset Value
0x00
0x00
0x00
0x00
Chapter 4. Configuration Registers
Memory Interface Configuration Registers
Description
Reserved
Extended starting address for bank 3
Reserved
Extended starting address for bank 2
Reserved
Extended starting address for bank 1
Reserved
Extended starting address for bank 0
Reserved
Extended starting address for bank 7
Reserved
Extended starting address for bank 6
Reserved
Extended starting address for bank 5
Reserved
Extended starting address for bank 4
16 15
8
16 15
8
Description
Ending address for bank 3
Ending address for bank 2
Ending address for bank 1
Ending address for bank 0
Byte Address
0x88
0x8C
7
0
7
0
Byte Address
0x90
4-25