Nmi (Nonmaskable Interrupt) - Motorola MPC8240 User Manual

Exception Latencies

13.3.3.5 NMI (Nonmaskable Interrupt)

If PICR1[MCP_EN] is set and a PCI agent asserts the NMI signal to the MPC8240, the
MPC8240 reports the error to the processor core by asserting mcp provided
PICR1[MCP_EN] is set.
When the NMI signal is asserted, no error flags are set in the status registers of the
MPC8240. The agent that drives NMI should provide the error flag for the system and the
mechanism to reset that error flag. The NMI signal should then remain asserted until the
error flag is cleared.
13.3.4 Message Unit Error Events
The inbound portion of the message unit can cause the assertion of mcp by a software
programmable flag. There are also two overflow events on the inbound message queues that
can cause the assertion of mcp. See Chapter 9, "Message Unit (with I2O)," for more
information on the message unit.
The MC bit in the IDBR allows a PCI master to generate a machine check interrupt (mcp)
to the processor core.
The IMISR contains the interrupt status of the I O, doorbell, and message register events.
2
These events are generated by PCI masters and are routed to the processor core from the
message unit with the internal int or mcp signals. The specific bits in the IMISR that can
cause mcp to be asserted are the outbound free_list overflow condition (OFO) and the
inbound post_list overflow condition (IPO). In addition, the doorbell machine check
condition IMISR[DMC] provides an indication that the IDBR[MC] bit has been set by a
PCI master.
The processor core interrupt handling software must service these interrupts and clear the
interrupt bits. Software attempting to determine the source of the interrupts should always
perform a logical AND between the IMISR bits and their corresponding mask bits in the
IMIMR.
13.4 Exception Latencies
Latencies for taking various exceptions depend on the state of the MPC8240 when the
conditions to produce an exception occur. The minimum latency is one cycle, in which case
the exception is signaled in the cycle after the exception condition occurs.
Chapter 13. Error Handling 13-11