Pci Bus Grant (Gnt[4:0])—Internal Arbiter Disabled - Motorola MPC8240 User Manual

signals are used in conjunction with the REQ[4:0] signals as the arbiter for up to five PCI
masters. Following is the state meaning for the GNT[4:0] input signals in this case.
State Meaning
2.2.1.2.2 PCI Bus Grant (GNT[4:0])—Internal Arbiter Disabled
The MPC8240 PCI arbiter is disabled by a high value on the reset configuration pin MAA2
or by the clearing of bit 15 of the PCI arbitration control register. In this case, the GNT0
becomes the PCI bus request output for the MPC8240 and is asserted when the MPC8240
needs to run a PCI transaction. If the REQ0 input signal is asserted prior to the need to run
a PCI transaction, then the GNT0 signal will not assert (the bus is parked) when a PCI
transaction is to be run. Following is the state meaning for the GNT[4:0] input signals when
the internal arbiter is disabled.
State Meaning
2.2.1.3 PCI Address/Data Bus (AD[31:0])
The PCI address/data bus (AD[31:0]) consists of 32 signals that are both input and output
signals on the MPC8240.
2.2.1.3.1 Address/Data (AD[31:0])—Output
Following is the state meaning for AD[31:0] as outputs.
State Meaning
2.2.1.3.2 Address/Data (AD[31:0])—Input
Following is the state meaning for AD[31:0] as inputs.
State Meaning
Asserted—The MPC8240 has granted control of the PCI bus to a
requesting master, using the priority scheme described in
Section 7.2, "PCI Bus Arbitration." The MPC8240 will assert only
one GNTn signal during any clock cycle.
Negated—Indicates that the MPC8240 has not granted control of the
PCI bus and external devices may not initiate a PCI transaction.
Asserted—The MPC8240 asserts the GNT0 signal as the PCI bus
request output signal. GNT[4:1] signals do not assert in this case.
Negated—The GNT[4:1] signals are driven high (negated) in this
mode. GNT0 is negated when the MPC8240 is not requesting control
of the PCI bus or the bus is parked on the MPC8240.
Asserted/Negated—Represents the physical address during the
address phase of a PCI transaction. During a data phase of a PCI
transaction, AD[31:0] contain data being written.
The AD[7:0] signals define the least-significant byte and AD[31:24]
the most-significant byte.
Asserted/Negated—Represents the address to be decoded as a check
for device select during an address phase of a PCI transaction or data
being received during a data phase of a PCI transaction.
Chapter 2. Signal Descriptions and Clocking
Detailed Signal Descriptions
2-9