Motorola MPC8240 User Manual page 335

Table 7-4. PCI Configuration Space Header Summary (Continued)
Address
Register Name
Offset (Hex)
0x0E Header type
0x0F BIST
0x10–0x27 Base address registers
0x28
0x2C
0x30 Expansion ROM base
address
0x34
0x38
0x3C Interrupt line
0x3D Interrupt pin
0x3E Min_Gnt
0x3F Max_Lat
7.4.5.2 Accessing the PCI Configuration Space
This section describes accessing the external PCI configuration space. See Section 7.7.2,
"Accessing the MPC8240 Configuration Space," for information on accessing the internal
configuration registers of the MPC8240.
To support hierarchical bridges, two types of configuration accesses are supported. The first
type of configuration access, type 0, is used to select a device on the local PCI bus. Type 0
configuration accesses are not propagated beyond the local PCI bus and must be claimed
by a local device or terminated with a master-abort. The second type of configuration
access, type 1, is used to pass a configuration request to another PCI bus (through a
PCI-to-PCI bridge). Type 1 accesses are ignored by all targets except PCI-to-PCI bridges.
To access the configuration space, a 32-bit value must be written to the CONFIG_ADDR
register that specifies the target PCI bus, the target device on that bus, and the configuration
register to be accessed within that device. A read or write to the CONFIG_DATA register
causes the host bridge to translate the access into a PCI configuration cycle (provided the
enable bit in CONFIG_ADDR is set and the device number is not 0b1_1111).
For the MPC8240, the CONFIG_ADDR register is located at different addresses depending
on the memory address map in use. The address maps are described in Chapter 3, "Address
Maps." For address map B, the processor can access the CONFIG_ADDR register at any
location in the address range from 0xFEC0_0000 to 0xFEDF_FFFF. For simplicity, the
address for CONFIG_ADDR is sometimes referred to as CF8, 0xnnnn_nCF8, or (in the
PCI literature as) CF8h. Although systems implementing address map B can use any
Bits 0–6 identify the layout of bytes 10–3F; bit 7 indicates a multifunction
device. The most common header type (0x00) is shown in Figure 7-8 and
in this table.
Optional register for control and status of built-in self test (BIST)
Address mapping information for memory and I/O space
— Reserved for future use
— Reserved for future use
Base address and size information for expansion ROM contained in an
add-on board
— Reserved for future use
— Reserved for future use
Contains interrupt line routing information
Indicates which interrupt pin the device (or function) uses
Specifies the length of the device's burst period in 0.25 µs units
Specifies how often the device needs to gain access to the bus in 0.25
µs units
Chapter 7. PCI Bus Interface
PCI Bus Transactions
Description
7-23