Integrated Pci Bus And Sdram Clock Generation - Motorola MPC8240 User Manual

The module operates in one of three modes:
• In direct mode, five level- or edge-triggered interrupts can be connected directly to
an MPC8240.
• In pass-through mode, interrupts detected at the IRQ0 input are passed directly to
the processor core. Also in this case, interrupts generated by the I
controllers are passed to the L_INT output signal.
• The MPC8240 provides a serial delivery mechanism when more than five external
interrupt sources are needed. The serial mechanism allows for up to 16 interrupts to
be serially scanned into the MPC8240. This mechanism increases the number of
interrupts without increasing the number of pins.
The outbound interrupt request signal, L_INT, is used to signal interrupts to the host
processor when the MPC8240 is configured for agent mode. The MPC8240 EPIC includes
four programmable timers that can be used for system timing or for generating periodic
interrupts.

1.4.9 Integrated PCI Bus and SDRAM Clock Generation

There are two PCI bus clocking solutions directed towards different system requirements.
For systems where the MPC8240 is the host controller with a minimum number of clock
loads, five clock fanout buffers are provided on-chip.
For systems requiring more clock fan out or where the MPC8240 is an agent device,
external clock buffers may be used.
The MPC8240 provides an on-chip delay-locked loop (DLL) that supplies the external
memory bus clock signals to SDRAM banks. The memory bus clock signals are of the same
frequency and synchronous with the internal peripheral bus clock.
The four SDRAM clock outputs are generated by the internal DLL and can account for the
trace length between SDRAM_SYNC_OUT signal and the SDRAM_SYNC_IN signal.
The MPC8240 requires a single clock input signal, PCI_SYNC_IN, which can be driven
by the PCI clock fan-out buffers—specifically the PCI_SYNC_OUT output.
PCI_SYNC_IN can also be driven by an external clock driver.
PCI_SYNC_IN is driven by the PCI bus frequency. An internal PLL, using PCI_SYNC_IN
as a reference, generates an internal sys-logic-clk signal that is used for the internal logic.
The peripheral bus clock frequency is configured at reset (by the MPC8240 PLL
configuration signals (PLL_CFG[0:4])) to be a multiple of the PCI_SYNC_IN frequency.
The internal clocking of the processor core is generated from and synchronized to the
internal peripheral bus clock by means of a second PLL. The core's PLL provides multiples
of the internal processor core clock rates as specified in the MPC8240 Hardware
Specification.
Chapter 1. Overview
Peripheral Logic Overview
2
O, I C, and DMA
2
1-17