Memory Control Configuration Register 3 (Mccr3)—0Xf8 - Motorola MPC8240 User Manual

Memory Control Configuration Registers
Table 4-39. Bit Settings for MCCR2—0xF4 (Continued)
Bits Name
15–2 REFINT
1 RSV_PG
0 RMW_PAR
Figure 4-31 and Table 4-40 show memory control configuration register 3 (MCCR3)
format and bit settings.
BSTOPRE[2–5]
REFREC
31 28 27
Figure 4-31. Memory Control Configuration Register 3 (MCCR3)—0xF8
4-48
Reset
Value
All 0s Refresh interval. These bits directly represent the number of clock cycles between
CBR refresh cycles. One row is refreshed in each RAM bank during each CBR
refresh cycle. The value for REFINT depends on the specific RAMs used and the
operating frequency of the MPC8240. See Section 6.3.10, "FPM or EDO DRAM
Refresh," or Section 6.2.12, "SDRAM Refresh," for more information. Note that the
period of the refresh interval must be greater than the read/write access time to
ensure that read/write operations complete successfully.
0 Reserve page register. If this bit is set, the MPC8240 reserves one of the four page
registers at all times. This is equivalent to only allowing three simultaneous open
pages.
0 Four open page mode (default)
1 Reserve one of the four page registers at all times
0 Read-modify-write (RMW) parity enable. This bit controls how the MPC8240 writes
parity bits to DRAM/EDO/SDRAM. Note that this bit does not enable parity
checking and generation. PCKEN must be set to enable parity checking. Also note
that this bit and ECC_EN cannot both be set to 1. See Section 6.3.8, "FPM or EDO
DRAM Parity and RMW Parity," and Section 6.2.9, "SDRAM Parity and RMW
Parity," for more information.
0 RMW parity disabled
1 RMW parity enabled. Note that this bit must be set for SDRAM systems that use
in-line ECC (MCCR2[ECC_EN] = 0, MCCR4[BUF_TYPE[0–1]] = 0b10, and
MCCR2[INLINE_PAR_NOT_ECC]] = 0).
CPX
RDLAT
24 23 20 19 18
MPC8240 Integrated Processor User's Manual
Description
RAS CAS CP
6P 5 4
15 14 12 11
CAS RCD RP
3 2
9 8 6 5 3 2
1
0