Motorola MPC8240 User Manual page 132

Configuration Register Access
byte-swap the CONFIG_ADDR and CONFIG_DATA values before performing an access
(that is, software loads the configuration register address and the configuration register data
into the processor register in ascending byte order—LSB to MSB).
Note that in the following examples, the data in the configuration register (at 0xA8) is
shown in little-endian order. This is because all the internal registers are intrinsically
little-endian.
Example: Map B address map configuration sequence, 4-byte data write to register at
address offset 0xAA using store word with byte reversed instructions
Initial values:r0 contains 0x8000_00A8
r1 contains 0xFEC0_0000
r2 contains 0xFEE0_0000
r3 contains 0xAABB_CCDD
Register at 0xA8 contains 0xFFFF_FFFF (AB to A8)
Code sequence: stwbrx
sync
stwbrx
sync
Results:Address 0xFEC0_0000 contains 0x8000_00A8 (MSB to LSB)
Register at 0xA8 contains 0xAABB_CCDD (AB to A8)
Example: Map B address map configuration sequence, 2-byte data write to register at
address offset 0xAA, using byte-swapped values in the processor registers
Initial values:r0 contains 0xA800_0080
r1 contains 0xFEC0_0000
r2 contains 0xFEE0_0000
r3 contains 0xDDCC_BBAA
Register at 0xA8 contains 0xFFFF_FFFF (AB to A8)
Code sequence: stw
sync
sth
sync
Results:Address 0xFEC0_0000 contains 0x8000_00A8 (MSB to LSB)
Register at 0xA8 contains 0xAABB_FFFF (AB to A8)
Example: Map A configuration sequence, 2-byte data write to register at address offset
0xA8, using store with byte-reversed instructions
Initial values:r0 contains 0x8000_00A8
r1 contains 0x8000_0CF8
r2 contains 0xAABB_CCDD
r3 contains 0x8000_0CFC
Register at 0xA8 contains 0xFFFF_FFFF (AB to A8)
Code sequence: stwbrx
sync
sthbrx
sync
Results:Address 0x8000_0CF8 contains 0x8000_0004 (MSB to LSB)
Register at 0xA8 contains 0xFFFF_CCDD (AB to A8)
4-4
r0,0,r1
r3,0,r2
r0,0(r1)
r3,2(r2)
r0,0,r1
r2,0,r3
MPC8240 Integrated Processor User's Manual