Clock Synchronization - Motorola MPC8240 User Manual

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I C Protocol
shortest one among the masters. A bus master loses arbitration if it transmits a logic 1 on
SDA while another master transmits a logic 0. The losing masters immediately switch over
to slave-receive mode and stop driving the SDA line. In this case, the transition from master
to slave mode does not generate a STOP condition. Meanwhile, the I
I2CSR[MAL] status bit to indicate the loss of arbitration and, as a slave, services the
transaction if it is directed to itself.
Arbitration is lost (and I2CSR[MAL] is set) in the following circumstances:
• SDA sampled as low when the master drives a high during address or data-transmit
cycle.
• SDA sampled as low when the master drives a high during the acknowledge bit of a
data-receive cycle.
• A START condition is attempted when the bus is busy.
• A repeated START condition is requested in slave mode.
Note that the MPC8240 does not automatically retry a failed transfer attempt.
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If the I C module of the MPC8240 is enabled in the middle of an ongoing byte transfer, the
interface behaves as follows:
• Slave mode—the MPC8240 ignores the current transfer on the bus and starts
operating whenever a subsequent START condition is detected.
• Master mode—the MPC8240 will not be aware that the bus is busy; therefore, if a
START condition is initiated, the current bus cycle can become corrupt. This
ultimately results in the current bus master of the I
after which bus operations return to normal.

10.2.7 Clock Synchronization

Due to the wire AND logic on the SCL line, a high-to-low transition on the SCL line affects
all the devices connected on the bus. The devices begin counting their low period when the
master drives the SCL line low. Once a device has driven SCL low, it holds the SCL line
low until the clock high state is reached. However, the change of low-to-high in a device
clock may not change the state of the SCL line if another device is still within its low period.
Therefore, synchronized clock SCL is held low by the device with the longest low period.
Devices with shorter low periods enter a high wait state during this time. When all devices
concerned have counted off their low period, the synchronized SCL line is released and
pulled high. Then there is no difference between the devices' clocks and the state of the
SCL line, and all the devices begin counting their high periods. The first device to complete
its high period pulls the SCL line low again.
10-6 MPC8240 Integrated Processor User's Manual
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C unit sets the
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C interface losing arbitration,