A-2 Map A—Pci Memory Master View - Motorola MPC8240 User Manual

Address Space for Map A
PCI Memory Transactions Address Range
Hex
0000_0000 7FFF_FFFF
8000_0000 BFFF_FFFF
C000_0000 FEFF_FFFF
FF00_0000 FFFF_FFFF
Table A-3. Address Map A—PCI I/O Master View
PCI I/O Transactions Address Range
Hex
0000_0000 0000_FFFF
0001_0000 007F_FFFF
0080_0000 3F7F_FFFF
3F80_0000 3FFF_FFFF
4000_0000 FFFF_FFFF
Notes:
1 PCI configuration accesses to CF8 and CFC–CFF are handled as specified in the PCI Local Bus Specification.
See Section 7.4.5.2, "Accessing the PCI Configuration Space," for more information on how the MPC8240
accesses PCI configuration space.
2. Processor addresses are translated to PCI addresses as follows:
PCI address (AD[31:0]) = 0b0 || A[1:31]. PCI configuration accesses use processor addresses
0x8000_0CF8 and 0x8000_0CFC–8000_0CFF.
Note that only 64 Kbytes (0x8000_0000–0x8000_FFFF) has been defined. The remainder of the region is
reserved for future use.
3. IDSEL for direct access method: 11 = 0x8080_08xx, 12 = 0x8080_10xx,..., 18 = 0x8084_00xx. See
Section 7.4.5.2, "Accessing the PCI Configuration Space."
4. If the ROM is local, the MPC8240 ROM interface handles the access to local ROM. If ROM is remote, then the
MPC8240 generates a PCI memory transaction in the range 0xFF00_0000 to 0xFFFF_FFFF.
5. If the ROM is local, this space is reserved and accesses to it cause a memory select/Flash write error. If the
ROM is remote, then this space maps to PCI memory space.
A-2
Table A-2. Map A—PCI Memory Master View
Decimal
0 2G - 1
2G 3G - 1
3G 4G - 16M - 1
4G - 16M 4G - 1
Decimal
0 64K - 1
64K 8M - 1
8M 1G - 8M - 1
1G - 8M 1G - 1
1G 4G - 1
MPC8240 Integrated Processor User's Manual
Processor Core
Address Range
No local memory cycle
0000_0000–3EFF_FFFF
No local memory cycle
No local memory cycle
Processor Core
Address Range
No local memory cycle Addressable by the processor
No local memory cycle Reserved
No local memory cycle Addressable by the processor
No local memory cycle Not addressable by the
processor
No local memory cycle Not addressable by the
processor
Definition
PCI memory space
Local memory space
Reserved (causes
memory select error)
ROM space (reserved if
5
ROM is local)
Definition
2