Error Detection Register 2 (Errdr2)—0Xc5 - Motorola MPC8240 User Manual

Figure 4-25 shows the bits for error detection register 2.
ECC Multibit Error
Invalid Error Address
Figure 4-25. Error Detection Register 2 (ErrDR2)—0xC5
Table 4-34 describes the bits of error detection register 2.
Table 4-34. Bit Settings for Error Detection Register 2 (ErrDR2)—0xC5
Bits Name
7 Invalid error address
6–4 —
3 ECC multi bit error
2 Processor memory
write parity error
1 —
0 Flash ROM write error
The PCI bus error status register latches the state of the PCI C/BE[3:0] signals when an
error is detected on the PCI bus as defined in Section 13.3.3, "PCI Interface Errors."
0 0 0
7 6 4
Reset
Value
0 This bit indicates whether the address stored in the processor/PCI error
address register is valid.
0 The address in the error address register is valid.
1 The address in the error address register is not valid.
000 Reserved
0 ECC multibit error
0 No ECC multi bit error detected
1 ECC multibit error detected
0 Processor memory write parity error (SDRAM with in-line parity checking
only).
0 No error detected
1 Processor memory write parity error detected
0 Reserved
0 Flash ROM write error
0 No error detected
1 The MPC8240 detected a write to Flash ROM when writes to
ROM/Flash are disabled.
Chapter 4. Configuration Registers
Error Handling Registers
Processor Memory Write
Parity Error
Flash ROM Write Error
0
3 2 1 0
Description
Reserved
4-39