Sdram Page Mode - Motorola MPC8240 User Manual

from memory in the order 2-3-0-1. In 32-bit data bus mode, if the processor core requests
the third double word of a cache block, the MPC8240 reads words from memory in the
order 4-5-6-7-0-1-2-3.
For single-beat read transactions, the MPC8240 masks the extraneous data in the burst by
driving the DQM[0:7] signals high on the irrelevant cycles. For single-beat write
transactions, the MPC8240 protects non-targeted addresses by driving the DQM[0:7]
signals high on the irrelevant cycles. For single-beat transactions, the bursts cannot be
terminated early. That is, if the relevant data is in the first data phase, the subsequent data
phases of the burst must run to completion even though the data is irrelevant.

6.2.7 SDRAM Page Mode

Under certain conditions, the MPC8240 retains four active SDRAM pages for burst or
single-beat accesses. These conditions are as follows:
• A pending transaction (read or write) hits one of the currently active internal pages.
• There are no pending refreshes.
• The burst-to-precharge interval (controlled by BSTOPRE[0:9]) has not been
exceeded.
• The maximum activate-to-precharge interval (controlled by PGMAX) has not been
exceeded.
• MCCR2[RSV_PG] = 0b0. In this case only three active pages are allowed.
Note that the BSTOPRE[0:9] parameter is composed of BSTOPRE[0:1] (bits 19–18 of
MCCR4), BSTOPRE[2:5] (bits 31–28 of MCCR3), and BSTOPRE[6:9] (bits 3–0 of
MCCR4).
Page mode can dramatically reduce access latencies for page hits. Depending on the
memory system design and timing parameters, using page mode can save clock cycles from
subsequent burst accesses that hit in an active page. SDRAM page mode is controlled by
the BSTOPRE[0:9], and PGMAX parameters. Page mode is disabled by clearing the
PGMAX or BSTOPRE[0:9] parameters.
The page open duration counter is loaded with BSTOPRE[0:9] every time the page is
accessed (including page hits). When the counter expires (or when PGMAX expires) the
open page is closed with a precharge bank command. Page hits can occur at any time in the
interval specified by BSTOPRE.
The 1-byte memory page mode register (MPMR) contains the PGMAX parameter that
controls how long the MPC8240 retains the currently accessed page (row) in memory. The
PGMAX parameter specifies the activate-to-precharge interval (sometimes called row
active time or t ). The PGMAX value is multiplied by 64 to generate the actual number
RAS
of clock cycles for the interval. When PGMAX is programmed to 0x00, page mode is
disabled.
Chapter 6. MPC8240 Memory Interface
SDRAM Interface Operation
6-19