Standard Pci Configuration Header - Motorola MPC8240 User Manual

PCI Bus Transactions
BIST
Max_Lat
Figure 7-8. Standard PCI Configuration Header
Table 7-4 summarizes the registers of the configuration header. Detailed descriptions of
these registers are provided in the PCI Local Bus Specification, rev 2.1.
Table 7-4. PCI Configuration Space Header Summary
Address
Register Name
Offset (Hex)
0x00 Vendor ID
0x02 Device ID
0x04 Command
0x06 Status
0x08 Revision ID
0x09 Class code
0x0C Cache line size
0x0D Latency timer
7-22
Device ID
Status
Class Code
Header Type
Base Address Registers
Reserved
Reserved
Expansion ROM Base Address
Reserved
Reserved
Min_Gnt
Identifies the manufacturer of the device (assigned by the PCI SIG
(special-interest group) to ensure uniqueness)
Identifies the particular device (assigned by the vendor)
Provides coarse control over a device's ability to generate and respond
to PCI bus cycles
Records status information for PCI bus-related events
Specifies a device-specific revision code (assigned by vendor)
Identifies the generic function of the device and (in some cases) a
specific register-level programming interface
Specifies the system cache line size in 32-bit units
Specifies the value of the latency timer in PCI bus clock units for the
device when acting as an initiator
MPC8240 Integrated Processor User's Manual
Vendor ID
Command
Latency Timer Cache Line Size
Interrupt Pin Interrupt Line
Description
Address
Offset
0x00
0x04
Revision ID 0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
0x38
0x3C