B-2 Processor Address Modification For Individual Aligned Scalars - Motorola MPC8240 User Manual

Little-Endian Mode
Table B-2. Processor Address Modification for Individual Aligned Scalars
Note that munging makes individually aligned scalars appear to the processor as stored in
little-endian byte order when, in fact, they are stored in big-endian order but at different
byte addresses within double words. Only the address is modified not the byte order.
The munged address is used by the memory interface of the MPC8240 to access local
memory. To provide true little-endian byte-ordering to the PCI bus, the MPC8240
unmunges the address to its original value and the byte lanes are reversed. The MPC8240
unmunges aligned addresses by XORing the three low-order address bits with a three-bit
value that depends on the length of the operand (1, 2, 3, 4, or 8 bytes), as shown in Table
B-3.
Table B-3. MPC8240 Address Modification for Individual Aligned Scalars
The MPC8240 also supports misaligned 2-byte transfers that do not cross word boundaries
in little-endian mode. The MPC8240 XORs the address with 0x100. Note that the
MPC8240 does not support 2-byte transfers that cross word boundaries in little-endian
mode.
The byte lane translation for little-endian mode is shown in Table B-4.
Table B-4. Byte Lane Translation in Little-Endian Mode
Processor
Byte Lane
0
1
2
3
B-6
Data Length
(in Bytes)
8
4
2
1
Data Length
(in Bytes)
8
4
3
2
1
Processor Data Bus
Signals
DH[0–7]
DH[8–15]
DH[16–23]
DH[24–31]
MPC8240 Integrated Processor User's Manual
Address Modification
A[29–31]
No change
XOR with 0b100
XOR with 0b110
XOR with 0b111
Address Modification
A[29–31]
No change
XOR with 0b100
XOR with 0b101
XOR with 0b110
XOR with 0b111
PCI Address/Data Bus
PCI Byte Lane Signals During PCI Data
3
2
1
0
Phase
AD[31–24]
AD[23–16]
AD[15–8]
AD[7–0]