Processor Responses To Pci-To-Memory Transactions - Motorola MPC8240 User Manual

Table 5-5. CCU Responses to Processor Transactions (Continued)
Processor Transaction
stwcx., reservation set
tlbsync
Graphic write (ecowx)
Graphic read (eciwx)

5.4.3.2 Processor Responses to PCI-to-Memory Transactions

The CCU controls the data flow between the PCI interface and the memory interface. One
of its functions is to broadcast these transactions on the peripheral logic bus so that the
processor core can snoop the L1 cache as needed (if snooping is enabled). Table 5-5 shows
all the types of transactions reflected by the CCU to the processor core for snooping.
Table 5-6. Transactions Reflected to the Processor for Snooping
Snooped Transaction
Read
Read-with-intent-to-mo
dify (RWITM)-atomic
Condition Detected by CCU
Non-locked PCI read from memory
Locked PCI read from memory
Chapter 5. PowerPC Processor Core
CCU Response
CCU takes no further action.
(The MPC8240 does not support atomic
references in PCI memory space.)
CCU takes no further action.
Processor transaction error. Machine check
signalled to processor core (if enabled)
Processor transaction error. Machine check
signalled to processor core (if enabled)
Processor Response
All burst reads observed on the bus are
snooped as if they were writes, causing the
addressed cache block to be flushed. A read
marked as global causes the following
responses:
• If the addressed block in the cache is invalid,
the processor takes no action.
• If the addressed block in the cache is in the
exclusive state, the block is invalidated.
• If the addressed block in the cache is in the
modified state, the block is flushed to memory
and the block is invalidated.
A RWITM operation is issued to acquire
exclusive use of a memory location for the
purpose of modifying it.
• If the addressed block is invalid, the
processor takes no action.
• If the addressed block in the cache is in the
exclusive state, the processor changes the
state of the cache block to invalid.
• If the addressed block in the cache is in the
modified state, the block is flushed to memory
and the block is invalidated.
Cache Implementation
5-25