Inbound Fifos - Motorola MPC8240 User Manual

Figure 9-4 shows an example of the message queues:
Processor
Core Write
PCI Master
Read
Inbound
Queue
Port
PCI Master
Write
Processor
Core Read
Processor
Core Read
PCI Master
Write
Outbound
Queue
Port
PCI Master
Read
Processor
Core Write
Table 9-8 lists the queue starting addresses for the FIFOs.
Inbound free_list
Inbound post_list
Outbound post_list
Outbound free_list
The following subsections describe the inbound and outbound FIFOs of the I

9.3.3.1 Inbound FIFOs

The I O specification defines two inbound FIFOs—an inbound post_list FIFO and an
2
inbound free_list FIFO. The inbound FIFOs allow external PCI masters to post messages
to theMPC8240 processor core.
Head Pointer
Tail Pointer
Head
Pointer
Tail Pointer
Head
Pointer
Tail
Pointer
Head
Pointer
Tail
Pointer
Local Memory
Figure 9-4. I O Message Queue Example
2
Table 9-8. Queue Starting Address
FIFO
QBA (specified in QBAR)
QBA + (1*FIFO size specified in MUCR)
QBA + (2*FIFO size specified in MUCR)
QBA + (3*FIFO size specified in MUCR)
Chapter 9. Message Unit (with I
Inbound
Free List
FIFO
MFA
MFA
MFA
Inbound
Post List
FIFO
MFA
MFA
MFA
MFA
MFA
Outbound
Free List
FIFO
MFA
MFA
MFA
Outbound
Post List
FIFO
MFA
MFA
MFA
MFA
MFA
Starting Address
O)
2
I O Interface
2
Message
Frame
Message
Frame
Message
Frame
Message
Frame
Message
Frame
Message
Frame
Message
Frame
Message
Frame
Message
Frame
Message
Frame
Message
Frame
Message
Frame
Message
Frame
Message
Frame
Message
Frame
Message
Frame
System Memory
O interface.
2
9-7